ARM versus Intel: a successful stratagem for RISC or grist for CISC's tricks?

ARM and its licensees are striving to expand their overall market presence by tackling Intel’s x86 in servers and client desktop and laptop computers. Intel has responded by attacking ARM on its own turf: handsets, tablets, and the like.

Brian Dipert, Senior Technical Editor -- EDN, April 7, 2011

Since ARM unveiled the Version 7 instruction set, the company has subdivided its product line into three segments: the highly integrated Cortex-A application processors for mobile devices, cost-sensitive Cortex-M processors for traditional microcontroller applications, and high-performance Cortex-R processors for deeply embedded real-time applications. Cellular handsets, multimedia record-and-playback devices, and other portable electronics systems incur substantial product volume shipments. That fact, along with their direct competition with Intel-architecture processors, explains why this article focuses on ARM Cortex-A CPUs (see sidebar “Intel’s potential multiphase response”). For more, see EDN’s coverage of Cortex-M, Cortex-R, and alternative- market Cortex-A products, such as Ambarella’s iOne (Reference 1).

Arming for battle

Any discussion of ARM’s potential success in currently x86-dominated ecosystems must begin with an understanding of ARM’s business model and current product offerings. From a fiscal viewpoint, as an IP (intellectual-property) developer, ARM depends largely on the market success of its licensees, which fall into conventional- and architecture-license camps. Conventional licensees implement predesigned cores in their SOC (system-on-chip) designs, a more straightforward path to bringing products to market, which conversely limits each licensee’s ability to differentiate its products from those of competitors. Architecture, or instruction-set, licensees, on the other hand, have more design flexibility but also incur incremental corresponding design challenges. Although they must, as their name implies, retain full ARM instruction-set backward compatibility, they can also build on that suite with proprietary instructions, as well as make other more fundamental circuit alterations and enhancements. ARM currently has few architecture licensees, including Intel, Marvell, Microsoft, Nvidia, and Qualcomm, for example.


Conventional licensees’ core-implementation constraints don’t rule out notable innovations. Take, for example, the Fast14 dynamic-logic and signalencoding techniques that Samsung licensed from Intrinsity for use in Samsung’s Cortex-A8-based Hummingbird SOC. After acquiring Intrinsity a year ago, Apple subsequently implemented those techniques in its Cortex-A8-based A4 CPU. Fast14 enabled both Apple and Samsung, which also acted as the A4 SOC’s foundry source, to obtain notably higher clock speeds at a given process node than other Cortex-A8 licensees could accomplish. Conversely, architectural licensee Qualcomm developed the ARM Version 7-compliant Scorpion architecture, which, initially on 65-nm lithography, is currently in 45 nm.

Scorpion achieved dual-core status in mid-2010 with the 1.2-GHz MSM8260 and MSM8660. Functionally, it is an intermediary step between Cortex-A8 and Cortex-A9, supporting some but not all of Cortex-A9’s out-of-order instruction-execution capabilities. Scorpion-based Snapdragon SOCs also implement Cortex-A8- and A9-compliant floating-point and Neon SIMD engines. Scorpion implements the floating-point engine in a pipelined fashion, and the SIMD engine, at 128 bits, is twice as wide as the one in Cortex-A9.

Two generic terms, “application processor” and “baseband processor,” bear mentioning, although in practice they are becoming increasingly irrelevant, thanks to single-die integration trends. An application processor, as a seminal 2004 presentation from BDTI (Berkeley Design Technology Inc) describes, runs user applications, supports complex operating systems, emphasizes multimedia processing, supports Java and other virtual machines, and implements security features (Reference 2). The companion baseband processor, on the other hand, tackles wireless communications, including various cellular voice and data protocols.

Various ARM licensees have divergent perspectives on baseband- versus application-processor segmentation. Texas Instruments, for example, announced in October 2008 that it would phase out its participation in the baseband business, which it viewed as highly commoditized and therefore insufficiently profitable. Qualcomm, on the other hand, has embedded baseband capabilities within most of its Snapdragon CPUs, befitting the company’s MSM (Mobile Station Modem, formerly QSD for Qualcomm Semiconductor) product-name prefix, although some basebandless APQ (Application Processor Qualcomm) devices also exist. Nvidia, conversely, has been adamant that it makes no sense to burden the silicon area or constrain the technology development of an application processor with baseband capabilities. It may also make little sense to put a cellular-cognizant application processor into, for example, an optionally or by-default Wi-Fi-only tablet-computer design, therefore explaining, for example, the dual-core 1.2-GHz Qualcomm APQ8060 in Hewlett-Packard’s first-generation TouchPad tablet.

A focus on multimedia

Nvidia obtained notable aspects of its ARM-SOC program through the acquisitions of MediaQ, which it announced in August 2003, and of PortalPlayer, which it announced in November 2006. The company’s initial ARM11-based Tegra SOCs achieved limited market success, aside from being the processing nexus of Microsoft’s Zune HD portable multimedia player and short-lived Kin cellular handset. The company bypassed both the Cortex-A5 and the Cortex-A8 generations to come up with its next-generation Tegra 2 products, which it formally unveiled at the January 2010 CES. A year ago, Nvidia had a somewhat-tarnished industry reputation because the raft of Tegra 2-based tablet computers and other devices that company Chief Executive Officer Jen-Hsun Huang claimed at CES would shortly materialize hadn’t done so.

What a difference a year makes. Nvidia had achieved first-to-market status in the dual-core Cortex-A9 generation by several quarters versus competitors such as Texas Instruments. In doing so, it gained Google’s nod in the reference design for tablet-targeted Android Version 3 Honeycomb (Figure 1). Several high-end smartphones that debuted at the 2011 iterations of CES and MWC (Mobile World Congress) in mid-February also harness its capabilities, although its reported inability to decode high-profile 1080p H.264-encoded video led to its 11th-hour replacement in the Boxee set-top-box design by Intel’s Atom-based CE4100 CPU. Similarly, LG chose a Texas Instruments OMAP (Open Multimedia Applications Platform) 4-based CPU for its Optimus 3-D handset, although Tegra 2 had received the nod in the Optimus 2X phone LG had introduced less than two months earlier. LG chose the OMAP 4 because TI’s SOC could encode 3-D content in real time in 1080p resolution, whereas Nvidia’s CPU had only 720p capabilities (references 3 and 4).

Tegra 2 comes in T20 and AP20 variants, encompassing the Tegra 230 and Tegra 250, respectively. Both CPUs run at 1 GHz, but the GPU (graphics-processing unit) in T20 uses a 333-MHz clock and DDR2 system memory, befitting the larger screens and batteries in tablets. Its handset-focused AP20 peer, in contrast, operates the GPU at 300 MHz and interfaces to the more-power-stingy LP (low-power) DDR2 SDRAM. Strictly speaking, it’s a triple-ARM configuration because it also contains an ARM7 core for overall SOC management. You can suspend both Cortex-A9 cores, albeit not individually, when, for example, only the audio, imaging, graphics, and other dedicated processing resources are in use (Figure 2).


The target per-core Cortex-A9 clock speed for Kal-El is 1.5 GHz. Unlike Tegra 2, Kal-El embeds a Neon SIMD vector FPU for each CPU core. Like Tegra 2, however, Kal-El continues to rely on a unified 1-Mbyte pool of L2 cache memory, which twice as many CPU cores as before share, as well as a 32-bit system-memory interface. The Nvidia-designed GPU is not only faster in Kal-El than in Tegra 2 but also ups the core count from eight to 12. Both Tegra 2 and Kal-El employ a 40-nm manufacturing process, thereby explaining the die-size boost from 49 mm² on Tegra 2 to roughly 80 mm² on Kal-El. Nvidia’s marketers believe that Kal-El will deliver roughly five times the aggregate speed of Tegra 2—twice the CPU performance and three times the graphics performance—and consume no more—and, in some cases, notably less—power on a workload-dependent, per-CPU core basis.

Nvidia executives optimistically claim that Kal-El will be in productiongrade tablets as early as August and that smartphone-inclusive products will be available in time for the holiday shopping season. Would-be customers and partners should use appropriate caution, however, considering overly enthusiastic corporate prognostications made in the past. Nvidia plans to introduce Kal-El successors, also with superhero- reminiscent names, on a yearly cadence, and the company claims that these products will lead to a roughly 100-times overall performance boost over Tegra 2 by 2014.

Mobile systems don’t encompass all of Nvidia’s ARM aspirations. The company recently boosted its SOC-license status to the architectural level, which it plans to harness on the supercomputer-targeted Project Denver. Company executives teased media attendees of CES about the existence of Denver, but industry observers don’t currently know much about it.

TI moves

Long-standing ARM licensee Texas Instruments has to date followed a predictable SOC-development path, combining ARM CPU cores with Imagination Technologies PowerVR graphics cores and, in some cases, augmenting the cores’ capabilities with internally developed dedicated-function logic blocks and general-purpose DSP resources. A traditional early adopter of each new ARM-core iteration, the company has admitted that it was late to the Cortex-A9—that is, OMAP 4—era, thereby opening the door for competitors such as Nvidia. Judging from the flurry of recent product announcements and customer adoptions, TI seems disinclined to repeat the same mistake.

Take OMAP 4, for example. TI announced at MWC that it was shipping the initial product-family member, the OMAP 4430, in production volumes, for use in systems such as the LG Optimus 3D and the first tablet from RIM (Research in Motion), the Black- Berry PlayBook (Figure 3). Like Nvidia’s Tegra 2, the OMAP 4430 shares a common 1-Mbyte pool of L2 cache between two Cortex-A9 cores running at 1 GHz. However, the OMAP 4430 is also unique in several respects. For example, it employs a PowerVR SGX 540 GPU running at approximately 300 MHz—roughly 50% faster than that of competitors’ SGX 540-based SOCs. It also interfaces to system memory over two 32-bit LPDDR2 ports operating at speeds as high as 400 MHz, and each CPU core includes Neon SIMD vector floating-point capabilities in the form of ARM’s MPE (media-processing engine).

In December, TI also unveiled the more advanced OMAP 4440, which the company fabricates, like its 4430 sibling, on a 45-nm process. Available for sampling now, with production slated for the second half of this year, it runs the Cortex-A9 cores at 1.5 GHz and delivers a 25% increase in overall graphics performance, according to TI. Other enhancements include 60-frame/sec, 1080p video- decoding capabilities; support for as many as two 12M-pixel camera sensors; an HDMI (high-definition-multimedia-interface) 1.4 video output; and automatic stereoscopic 3-D displays. At MWC, TI highlighted these capabilities, along with gesture-based user interfaces and integrated DLP (digital-light-projector) features, as Me-D experiences that rationalized OMAP 4’s performance potential. The company also showcased Epos technology, which allows users to take notes and draw using a pen or a stylus. The writing tool comes with an Epos-patented ultrasonic transmitter, and the OMAP processor selects the transmitted signals using three microphones to accurately determine the location of the pen or the stylus. This approach allows users to take notes either on the screen or off screen next to the mobile device and with or without paper or ink, according to TI (Reference 5).

Texas Instruments also announced plans last August to support the Cortex-A15, or Eagle, core architecture. It’s probably no surprise, then, that the company was first to unveil product plans a week before MWC, even though the industry still knows little about Cortex-A15, aside from its support for extended memory addressing and hardware virtualization. TI implemented the core on a 28-nm process lithography and consolidated it under the OMAP 5 marketing umbrella. Initial Cortex-A15-based products will encompass two CPU cores running at frequencies as high as 2 GHz. Imagination Technologies’ PowerVR SGX 544 GPU handles graphics-processing tasks, although core counts and clock speeds are not yet public information.

OMAP 5 integrates dedicated function blocks for video, imaging and vision, digital-signal-processing, display, and security tasks. The SOC also dedicates two ARM Cortex-M4 processors to real-time processing. Like OMAP 4, its system-memory interface comprises two 32-bit channels in at least two technology variants. The OMAP 5430 comes in a 14×14-mm POP (package-on-package) module with LPDDR2 memory support, and the OMAP 5432 comes in a 17×17-mm BGA package and supports faster DDR3/DDR3L SDRAM. TI most likely is targeting the OMAP 5430 at smartphones and the 5432 at tablets. Regardless, Texas Instruments is clearly confident in ARM’s claims that Cortex-A15 applications can extend from servers to mobile systems. OMAP 5’s coreshared L2 cache size doubles from that of OMAP 4 to 2 Mbytes.

Internal SOC muscle

To some, the word “Apple” and the phrase “semiconductor supplier” may not automatically go together, but the company has a long history of designing chip sets for its 68K- and Power-PC-based Macs. Commensurate with the transition to Intel-architecture microprocessors, the company also turned over core-logic development to its new CPU partner. Apple has now redirected its IC focus on its ARM-based products, such as the iPad, iPhone, iPod touch, and second-generation Apple TV. Presumably, Apple decided that its high product-shipment volumes rationalized internal IC-design projects. Eliminating the middleman semiconductor supplier’s pricing markup would more than counterbalance these projects’ R&D costs. Two key corporate acquisitions—of PA Semi three years ago and of Intrinsity—fueled the development of Apple’s A4 SOC, which is currently in the iPhone 4, first-generation iPad, fourth-generation iPod touch, and second-generation Apple TV. Employing a single-core Cortex-A8 processor architecture, the A4 also embeds a PowerVR SGX 535 GPU and 640 kbytes of L2 cache memory. Its CPU clock frequency is system-dependent: 800 MHz on the iPod touch, for example, versus 1 GHz on the iPad.

The A4 CPU displaced Samsung-designed ARM SOCs in earlier iPhone and iPod touch systems. Ironically however, Samsung continues to act as Apple’s foundry for the A4 and supplies the DRAM in the SOC’s POP module. Equally ironic, Samsung’s S5PC110A01 Hummingbird SOC is similar to Apple’s A4, with the exception of Hummingbird’s L2-cache size of 512 kbytes and its inclusion of a PowerVR SGX 540 GPU versus the SGX 535 in the Apple A4. Die plots of the two ICs confirm that they’re unique designs; nonetheless, the common lineage is indisputable.

Like Apple, Samsung’s semiconductor group exclusively devotes its Hummingbird allocation to its handset division. At MWC, the company unveiled its latest-generation Galaxy S II highend smartphone, which it based on the next-generation Exynos SOC. The dual- core, 1-GHz, Cortex-A9-based Exynos SOC, formerly code-named Orion, migrates from the PowerVR graphics in Hummingbird to ARM’s own Mali 400MP GPU core (see sidebar “Graphics, the other key distinction for ARMbased SOCs”).

As it turns out, however, at least two versions of the Galaxy S II will exist. The GT-I9100 model uses Exynos. Reflecting the “may-not-be-applicable-in-some-regions” qualifier on the spec sheet, however, an equivalent GTI9103 variant employs the SOC engine of a semiconductor competitor, Nvidia’s Tegra 2 (Reference 6). Samsung also based its 10.1-in. variant of the Galaxy Tab tablet series on Tegra 2, although the 7-in. model employs Hummingbird. The reason for the twotier Galaxy S II differentiation is unclear, and Samsung isn’t forthcoming with an explanation. It might, for example, be a function of low initial Exynos product yields, or it may reflect limited Samsung fab capacity due to the amount of foundry supply that partner and competitor Apple consumes.


Flexible design

Marvell and Qualcomm have more design flexibility than their competitors by virtue of their ARM-architecture licenses. Qualcomm’s Scorpion microarchitecture has served the company well through several process-lithography generations, with many design wins over several years, across multiple customers, and across diverse mobile operating systems. However, its pseudo-Cortex-A9 performance capabilities have become dated in the era of true Cortex-A9 designs, especially the emerging multicore variants.

In response, Qualcomm chose February’s MWC to unveil Krait, its next-generation proprietary core, which retains compatibility with the ARM Version 7 instruction set. Initially targeting the 28-nm process node and running at per-CPU core speeds as high as 2.5 GHz, Krait will initially come in three product variants, each interfacing to system memory over a common dual-channel bus. It also serves as the launch platform for Qualcomm’s next-generation Adreno GPU cores. First to become available for sampling this quarter is the MSM8960, whose dual CPU cores are asynchronously and independently controllable. The MSM8960 also contains the Adreno 225, which Qualcomm claims delivers eight times the performance of the original Adreno core.

Following the MSM8960 to the sampling pedestal are two other Krait proliferations, both of which Qualcomm scheduled for initial availability in early 2012. The single-core MSM8930 mates with the Adreno 305, which should deliver more than six times the performance of the original Adreno. At the product family’s high end, the quad-CPU-core APQ8064 pairs with the integrated quad-core Adreno 320 GPU, with as much as 15 times the original Adreno’s capabilities. All product-family members will integrate Wi-Fi, GPS (global-positioning-system), Bluetooth, and FM connectivity transceivers and will support NFC (near-field communication) and autostereoscopic 3-D still-image and video capture and playback. MSM products will additionally include LTE (long-term-evolution)-only or 3G (third-generation)/LTE combo cellular modems.

Marvell obtained its ARM-architecture license by virtue of its 2003 purchase of Asica, and most of its design team through the mid-2006 acquisition of Intel’s ARM-based Xscale product line. Having expanded beyond its Intel-sourced PXA Series origins, the company’s products also subdivide into the 100, 300, 500, 600, and 1000 Armada-family tiers, with a variety of feature differentiations. They use either the ARM Version 5-compliant Sheeva PJ1 or the ARM versions 6- and 7-compliant Sheeva PJ4 CPU-core technology. Other differentiating features include the number of per-SOC cores, along with their clock speeds; cache sizes and the number of cache levels; system-memory-bus width and speed; the degree of on-chip graphics- and video-processing horsepower; and the variety and number of other integrated peripherals.

To date, Marvell has had limited success in the computing and communications applications that this article discusses, with the exception of being a key supplier to RIM. The company keeps trying, however. Last September, for example, Marvell unveiled the Armada 628, containing three Sheeva PJ4 Cortex-A9-class CPU cores in a nod to their two-issue, limited instruction-reordering capabilities. Two of the cores run at 1.5 GHz, the third clocks in at 624 MHz, and the on-chip graphics can process 200 million triangles/sec. Two months later, Marvell unveiled a quad-core, 1.6-GHz Sheeva PJ4-based SOC containing as much as 2 Mbytes of L2 cache and targeting servers. Curiously, though, at the January 2010 CES, the company had claimed that its first quad-core ARM device would serve the mass consumer market and high-volume gaming applications (Reference 7).

Speaking of the consumer market, Marvell at MWC announced the 40- nm-based PXA978 World Phone communications processor, running at 1.2 GHz and including a cellular-modem supporting 3G UMTS (Universal Mobile Telecommunications System) and China’s TD-SCDMA (time-division-synchronous-code-division/multiple access), with HSPA (high-speed-packet-access) support.

You can reach Senior Technical Editor Brian Dipert at 1-916-548-1225, brian.dipert@ubm.com, and www.bdipert.com.

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References

Dipert, Brian, “Ambarella’s iOne: augmenting an image-processing foundation with ever-increasing integration,” EDN, Dec 22, 2010. “Selecting Application Processors for Mobile Multimedia,” Berkeley Design Technology, 2004. Davies, Chris, “Optimus 3D vs Optimus Tab: Not all HD 3D video is created equal,” SlashGear, Feb 14, 2011. Dipert, Brian, “Coming soon: 3-D TV,” EDN, April 8, 2010, pg 24. “TI’s OMAP platform spurs Me-D experiences: Welcome to the next mobile dimension,” Texas Instruments, Feb 14, 2011. Galaxy S2 Specification, Samsung. “Marvell Announces Another Breakthrough in Chip Technology: World’s First Quadruple Core Processor for ARM Instruction Set,” Marvell, Jan 6, 2010.

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For More Information
Ambarella	AMD	Apple	ARM
BDTI	Boxee	Caustic Graphics	Hewlett-Packard
Imagination Technologies	Intel	LG Electronics	Marvell
Microsoft	MIPS	Motorola	NEC
Nokia	Nvidia	Qualcomm	Research In Motion
Samsung	ST-Ericsson	STMicroelectronics	Texas Instruments
Via Technologies	Vivante

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