KaiSemi claims automatic FPGA-to-ASIC conversion

Ron Wilson, Editor at large -- EDN, June 9, 2011

Using a variety of processes from 90 to 500 nm, fabless semiconductor vendor KaiSemi Ltd recently unveiled automated conversion, a process to convert most current FPGA designs to drop-in ASIC replacements. According to Tomer Kabakov, the company’s vice president of marketing, the flow begins with a design review. The customer provides a frozen FPGA netlist and an SDF (standard-delay-format) file; functional test vectors; pin definitions, including electrical requirements; and a checklist of additional information, such as timing constraints, clock frequencies, and test strategy. Kabakov notes that strong indicators of the convertibility of a netlist are the successful operation of the design in production and the completeness of the test-vector set. Beyond that, the review looks for known conversion obstacles, such as asynchronous blocks or multigigabit I/Os.

KaiSemi then runs its conversion tool. A run takes 12 to 24 hours, depending on the original design’s size. The tool transforms the FPGA netlist into a cell-based ASIC netlist using a proprietary set of libraries that KaiSemi developed for the purpose. This process is not a simple mapping of look-up tables, multiplexers, and registers into cells, Kabakov says. The tool infers logic functions from the FPGA netlist and attempts to map them into functional blocks from the libraries. KaiSemi also attempts to map third-party IP (intellectual-property) blocks directly rather than through netlist conversion.

The approach should not only produce better results for a random-logic netlist but also address two problems in conversion: block RAM and DSP blocks. The tool examines the configuration of block RAM and its wrapper in the FPGA netlist, infers the actual RAM function the design uses—a small multiport, say, or a large FIFO (first-in/first-out) buffer with overflow and underflow flags—and instantiates the correct function in the ASIC netlist. It does not attempt to replicate the block RAM itself.

Similarly, the tool examines the netlist’s use of FPGA DSP blocks and infers an optimized datapath. The cellbased netlist in KaiSemi’s older processes can usually keep up with the maximum clock rate the customer is applying to the nominally faster DSP block in the FPGA.

The flow moves from translation to formal and functional netlist verification and from there to a conventional ASIC back-end flow: scan/test insertion, resimulation, and physical design. By translating netlists rather than resynthesizing RTL (register-transfer-level) logic, KaiSemi stays closer to the original design and substantially shortens the front-end-design time. By inferring intent from the netlist, however, the tool escapes slavishly duplicating the FPGA-specific fine structure of look-up tables, registers, and hard-function blocks.

KaiSemi charges no NRE (nonrecurring-engineering) costs for the conversion service. The vendor calculates the unit price for the resulting ASIC based on the complexity of the design, the manufacturing cost, and the amortization of the cost conversion.

KaiSemi