Chip-and-package co-design relieves pressure on complex designs

Co-design accomplishes more with less by performing more design tasks in a shorter design cycle.

Darvin Edwards, Texas Instruments -- EDN, September 8, 2011

Enter co-design. Manufacturers should be constantly examining all aspects of design to verify that they are meeting all of the performance targets for final products. With each successive performance-target verification and fine-tuning, the overall value of the product to the user increases, and the risk of a failed product launch diminishes. The goal is to accomplish more with a shorter design cycle by concurrently executing more design tasks. Of course, one of the ultimate goals is that first prototypes will function to spec, avoiding the dreaded design re-spin. Failed products that require design re-spins are costly on many fronts for both semiconductor manufacturers and their customers.


Chip/package co-design

Chip-and-package co-design concurrently initiates package design with custom die and even system-level design. With this method, a team can quickly bring a new product to market and achieve the performance characteristics required to be competitive. In addition to the normal challenges that revolve around optimizing the performance characteristics of the eventual device, certain foundational challenges are inherent in every chip-and-package co-design effort. These challenges involve people working together and software tools that can share databases to quickly evaluate design characteristics.

At the beginning of a co-design project, all of the various design disciplines must come together. A chip-and-package co-design effort includes experts on all the elements in the silicon-production process, including transistor-design libraries, I/O (input/output) cells, packaging and materials, manufacturing and assembly, and chip test. Getting such a large group together may not involve a physical meeting of everyone on the team, but it must involve a merging of intentions for everyone. For the project to succeed, all of the key players from across all design areas must share the common goal of creating an optimized end product.

At the onset of the chip-and-package co-design project, representatives of each discipline must understand the chief needs of every other discipline. For example, the electrical-layout engineers must be aware of any thermal limitations in the package that could require a change in the placement of logic or I/O blocks to reduce operating temperatures. In addition, circuit designers must create any analog circuits that are sensitive to package-stress gradients with specific package limitations in mind.

Moreover, packages must supply the required number of I/Os for the chip layout, and manufacturability concerns may dictate specific rules so that the product meets the requirements of high-volume production. In the end, the team must be cognizant of the target cost of the product to avoid choosing too-expensive options. Some concerns of team members may evoke more passionate responses than others, but eventually the entire team must pull together around the common goal, which will come down to delivering a compelling and engaging experience for the end user of the product.

Management’s commitment to the project’s common goal and to co-design as part of achieving this goal is essential. Conflicts among groups and even individuals who make up the co-design team may occur. Management should encourage constructive debate with the objective of arriving at the most effective approach. The leaders of the effort must occasionally guide the direction of the team when it cannot reach unanimity among conflicting positions.

The common denominator

One of the basic characteristics of every co-design project is the necessity for design teams to concurrently complete their work on a part of the overall design while other teams are developing other aspects of the design. For example, one team may be developing a chip layout while another team is selecting and designing a package construction.

Selection of system parameters, such as the PCB (printed-circuit-board) area that is available for a device, may drive packaging decisions and, in turn, affect die layout. Software simulations might sometimes identify significant power usage in a portion of the circuit, and these simulations could drive the need for thermal enhancements in the package. When tight schedules eliminate any chance of prototyping the design, designers must quickly simulate accurate component connections if the team wants to have multiple options.

Simulation tools generate a model of the chip and its package to analyze how various design options will affect the parametric performance of the device. For example, a simulated model of the device might analyze how a change in the package affects the electrical noise on the power-and-ground plane of the device or how a change in the package might alter the temperature on part of the device. Modeling the effects of packaging options on a device’s I/Os is also critical. Not so many years ago, a complex device might involve only several hundred I/Os. Now, the number of I/Os on a complex SOC (system-on-chip) device could easily reach 2000 or 3000, all of which couple together. To end up with the best possible device, the modeling tool must be able to analyze how a change in a package-design parameter, such as a power plane, would electrically affect all of these I/Os.

This type of scenario can be daunting for software-simulation tools. During a co-design project, the speed and abilities of the tools environment are critical. The time window for considering various package innovations is usually narrow. A faster simulation tool produces more models over a shorter period, meaning that the design team can consider a greater number of options to find the best approach. For example, if the software tools require a week to generate a complete model of the device and the team faces a schedule milestone three weeks away, the team can consider only relatively few alternatives without disrupting the project’s overall time line.

In a perfect world, computational resources would not limit simulation. The team could characterize and understand the many interactions among the design parameters. Simulation would explore multiple routing options, material choices, reliability margins, cost minimizations, manufacturability studies, die-size minimizations, and power margins. Development-software systems would automatically adjust the chip, package, and system design until all parameters were optimal.

This scenario is the long-term dream for co-design. In reality, though, current software and hardware systems have limitations. As a result, designers use their expertise to input their best options. A finite number of simulations then point out the areas in which additional optimization may be necessary. Designers change the designs and validate the alterations.

Making the model

Engineers and technicians need time to describe a device, its package, and the system to the various analysis tools, slowing down modeling and affecting the effectiveness of a chip-and-package co-design project. To generate a simulated model of a device, the software tool must have a detailed description or a language-based model of the device. Changes to the device design should be simple to input because this approach eases optimization. Unfortunately, this scenario occurs infrequently.

Describing the device geometries and the package layout to one or more tools can be laborious and tedious. It is difficult to describe the 3-D world of a real chip, package, and system in the words of the computer-simulation tools. Designers must divide the 3-D geometry into many elements through “meshing.” Mathematical functions, which relate elements to surrounding elements, describe the parameters for modeling, producing many simultaneous equations for the computer to solve. The accuracy of the solution is dependent on the quality of the subdivision of the 3-D solid and on how well the individual elements capture the gradients of the fields to be calculated. The physics of a device design could require different types of meshes. Some may need only surface meshes, whereas others require full 3-D representations.

In most instances, models must capture the interfaces of one material to another, sometimes requiring that the mesh be continuous across the boundaries of all components or structures in the design. For example, the mesh of a circuit trace must be continuous with the mesh of the surrounding substrate’s polymer to calculate interfacial stresses. In addition, whenever someone makes a change to the design, designers must remesh it.

These tasks often prove too difficult for current software tools without significant human intervention guiding them and supplying knowledge to the software to identify the order the tool should take for meshing complex geometries. Because each area of physics involves different types of meshes, experts often must manually repeat this intensive process during various steps.

This type of human intervention adds little value to the design-optimization task. The software tools should use adaptive meshing to automate this repeated meshing and check the mesh against the physics of the problem to identify where mesh refinement is necessary and to generate an accurate result. Once adaptive meshing and other automation features become standard features of all analysis tools, the time to describe a device will become dramatically shorter.

Optimized packaging

Time to market is one of the primary forces that drives chip-and-package co-design projects. After all, time is money, and you can never regain missed opportunities in the market. Another good reason for chip-and-package co-design is to achieve a product that excels in the market. Poorly optimized designs don’t deliver the performance that users expect, often resulting in product recalls and loss of market share.

For example, a poorly optimized chip design might consume more power than the system can efficiently handle, necessitating more expensive cooling features. A design that uses less power for the same performance will achieve more market success in a portable-system application, in which battery life is a key consideration. Users prefer a smaller portable device with a low profile and small footprint over a larger device with the same features. Moreover, if one chip runs faster than another for the same performance and cost, the faster chip will likely win market share. In general, the chip-and-package co-design team will examine, analyze, and evaluate all of the electrical, thermal, and thermomechanical characteristics of a device and its package.

Electrical issues

One of the first concerns of chip and package designers is which chip-interconnection technology to use. Flip-chip interconnection can still be more expensive than a wire-bonded approach. A wire-bonded package that is compatible with the device’s I/O count, speed, and performance specifications can result in significant cost reductions over the lifetime of a device. To select the best alternative, teams do electrical analysis on those products whose performance requirements overlap the capabilities of wire-bond and flip-chip interconnections. The rest of the package design flows from this selection.

A primary concern is whether enough power is getting onto the device for it to function at its specified level. The device’s package plays a major role in this regard because the resistance, inductance, and capacitance of the power and ground pins can distort the supply of clean power to the chip, creating power and ground bounce or noise. Chip-and-package co-designers simulate the electrical design of chips and packages with an eye toward analyzing the electrical noise on the power and ground pins and planes.

The simulation software can highlight areas of high noise, inductance, current density, or resistance for optimization. A redesign can then minimize the problems. A simulation sometimes indicates that filtering capacitance is necessary to reduce power and ground noise. These analyses should also consider the power- and ground-distribution planes in the system-level PCB, or at least apply a valid simplification of the system-level planes as a boundary condition.


Thermal considerations

Every power-consuming device is also a small heater that requires a means of power dissipation. Often, when a component’s power consumption exceeds 1W, the thermal needs of the chip drive the package choice. An effective chip-and-package co-design team examines how to best design the device’s package to conduct heat away from the device and toward the underlying PCB or to a heat sink, depending on the system application.


Stress

Thermomechanical-stress issues as they relate to chip-and-package co-design involve the mechanical interaction of the die, the package, and the system. These issues affect the reliability of not just the chip but also the end-use device. For example, DSPs for wireless base stations must be able to withstand swings from the high temperatures of a desert to the extreme cold of an Alaskan winter or a high mountaintop. These extreme conditions must not cause delamination of the various package layers or fatal fatigue of the solder balls that make the electrical connection to the PCB. The base station is only as reliable as the DSP chips that operate it, and the interaction between the chip and its package affects the DSP chips’ reliability.

Thermomechanical analysis reveals whether the package’s stress gradient is the best for the chip’s parametric performance. This analysis is particularly important with analog chips because stress-related gradients across the device can create shifts in the parametric characteristics of the transistors or resistors, resulting in deviations in the linearity, gain, voltage offset, and other characteristics of the device.

A chip-package analysis of the mechanical robustness of a device might lead to the deployment of a different material in the package or the inclusion of a structural element in the device. For example, process engineers work to implement new on-chip dielectrics in semiconductors because these materials reduce capacitance between the lines on a chip and enable higher switching speeds. These dielectrics are sometimes less dense and less structurally robust than other materials, however. The chip-and-package co-design team would need to simulate a new dielectric in the device to analyze whether the chip would be able to withstand a certain level of mechanical stress. Dangerously high levels of stress in the predictions might trigger a materials change or a new design rule to structurally strengthen the device.

Warping is another important concern for thermomechanical co-design engineers. Packages are laminates of multiple layers of different materials, each with its own expansion and stiffness. Passage through a temperature cycle can cause warping, which can in turn cause the package’s leads or solder balls either to not contact the PCB during soldering or to put too much pressure on the joint, which could result in solder bridging. Thermomechanical analysis can predict this warping and point out the need for different materials or structures if the warping is too severe. Shadow moiré, a measurement tool, further characterizes the warping and validates the thermomechanical modeling.

Calibration and validation

In many regards, chip-and-package co-design depends on modeling and other tools to simulate either portions of a design or the entire device so that the design team can study the effects of various design options, eventually resulting in a fully optimized design. The outcome of a chip-and-package co-design effort will be successful only if the tool’s outputs are accurate. A tool that returns an inaccurate result can wreak more havoc on a chip-and-package co-design project than having no result at all. The design team could take the wrong path by using faulty simulation information and not realize the mistake until the project has progressed significantly along its time lines. The team can never recoup the wasted time.

Because of these issues, experienced co-design teams constantly calibrate and validate the tools that are essential to the process. The most fundamental way of completing this task is to analyze the characteristics of devices both before and after manufacturing. Any discrepancy indicates a tool in need of recalibration.

When feasible, designers can plan test dice early in the process to place known stresses on sensitive components. These test dice can contain structures such as strain gauges, thermal sensors, leakage sensors, and variations on design rules. The test structures come early in the development process to enable calibration of the simulation tools before designers must use the tools for the driver products.

As investigators stress the test structures, they compare the devices’ outputs with the results from the simulation tools. When discrepancies exist, some degree of destructive analysis further characterizes the test structures and identifies the cause of the discrepancy. When the team identifies the causes, the members adjust the tools to match the test-structure results.

Co-design’s impact

The pressures on design teams will continue to grow in the foreseeable future as the electronic content in everyday devices, machinery, office equipment, consumer gadgets, medical systems, home appliances, and transportation vehicles accelerates in the years ahead. This acceleration heightens the design risks for system manufacturers and highlights the critical importance of all aspects of co-design. Extending the well-documented benefits of co-design into the realm of chip-and-package design will become increasingly imperative with so much riding on each design project.

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