Converters yield droop-free S/H circuit
Use an ADC and DAC back-to-back to process signals up to 1 kHz.
TG Barnett, The London Hospital Medical College, London, UK -- EDN, November 17, 2011
Originally published in the January 23, 1986, issue of EDN
In low-frequency applications, many monolithic sample/hold circuits suffer a droop rate that can cause an unacceptably large output error. The S/H circuit in Fig 1 eliminates droop error by operating two 8-bit multifunction converters back to back. The circuit requires a 5V supply and accepts analog inputs between 0 and 2.5V (although you can scale and offset any input signal to fall within this range).
The analog input is applied to the
inverting input of an LM324 op amp
(IC1), which is wired as a comparator.
The op amp and the IC2 multifunction
converter form a ramp-and-compare
A/D converter. (Because the
Ferranti ZN435 multifunction converter
includes a voltage-output D/A
converter, an 8-bit up/down counter,
a 2.5V bandgap reference, and a clock
generator, you can configure the device
either as an A/D or as a D/A converter.)
The converter’s internal counter counts
from 0, producing a positive-going ramp
at the analog output.When the ramp voltage exceeds
the analog input, the comparator output
goes high and sets IC5’s Q1 output
high, thus inhibiting IC2’s clock
and stopping the counter. IC2’s digital
outputs are connected to the digital
inputs of IC3, which is wired as a
D/A converter. The D/A converter provides the S/H circuit’s analog output.
The output will remain in a hold
state until you reset the monostable
multivibrator (IC4), whose outputs
apply simultaneous reset pulses to IC2
and IC5. The circuit then resamples and
holds a new value of analog input. The
S/H circuit provides 8-bit hold accuracy
for analog input frequencies as high as
1 kHz; you can use a faster op amp for
IC1 for higher-frequency operation.Talkback
