3-D IC standards are great, but do we care?
When it comes to 3-D ICs, when all is said and done, there's more said than done.
Patrick Mannion, Director of Content -- EDN, December 1, 2011
Next month’s DesignCon 2012, which will take place in
Santa Clara, CA, will host many interesting panels, including
“Why do we need 3-D design standards?” As cutting
edge and exciting as that title sounds, it may be asking the
wrong question, however. The right question may be, Do
the economics of 3-D make sense, and who takes the fall
when things go wrong?Many people have written volumes about 3-D IC packaging; EDN also recently covered it (Reference 1). As the old saying goes, “When all’s said and done, there’s more said than done.” With regard to 3-D ICs, alas, this saying is particularly true. Chi-Ping Hsu, PhD, senior vice president of Cadence’s Silicon Realization Group, sums it up. Although acknowledging it makes sense in certain applications, such as mobile devices, and with vertically integrated manufacturers, such as Intel, Hsu suggests the problem elsewhere comes down to the almighty dollar—and the blame game.
“Why [do it]?” asks Hsu. “Who is
accountable, and who makes the money
and at what stage?” Knowing that different
silicon sources have different ways of
manufacturing TSVs (through-silicon
vias), “who’s fault is it when you have
three dice, and it doesn’t work?” he adds.Other issues include handling fragile KGD (known-good die) and rework when things go awry. With multichip modules, the handling of KGD was a problem, but you could at least swap out a module if it were defective. That approach is more difficult with tightly packaged die with 10,000 interconnects per die. For now, according to Hsu, 2.5-D technology with bumped die on an interposer with associated logic is the way to go because it allows for rework and avoids the economics and the blame game.
Hsu’s pragmatism quickly leads us to a brief discussion of more practical approaches to today’s problems and to what may have been one of the least-hyped announcements of the year. While all media eyes this year were on 3-D IC design, Cadence was continuing to update Virtuoso IC 6.1, which includes the OA (Open Access) database. (Cadence developed OA and donated it to Si2, the Silicon Integration Initiative.) Users had previously been employing the CDB (Cadence database); the move to OA allowed design teams to save data in a format that other EDA vendors’ tools could use.
According to Hsu, the move to OA is a move to a new generation of technology that shifts designers from connectivity- based design to intent-based design by abstracting them from the underlying details. “We want designers to focus on creativity versus engineering,” he says. The end result is a 40% savings in project time, according to Hsu. The approach does raise questions, however, about what students preparing for the work force will require, but that topic is a separate discussion.
So, although 3-D may not be ready
for prime time, and EDA companies—wisely, I might add—focus on problems
resolvable and practical in the here
and the now, the DesignCon panel
does explore a key issue for 3-D enablement—
namely, the need for IC standards
to accelerate the adoption of 3-D
design. It will look at how the standards
can be implemented, the priority of
those standards, the challenges, and how
the industry is meeting those challenges.Those ideas may whet your appetite for the rest of the conference, which features a track focusing on analog and mixed-signal design and verification and tracks on system chip, board, and package co-design and chip-level design for signal and power integrity. The panel on 3-D standards is part of the system-co-design track and features as speakers Sumit DasGupta from Si2, Liam Madden from Xilinx, and Raj Jammy from Sematech.
I’ll be at this year’s conference looking for both leading-edge explorations and practical approaches to real-world problems. See you there.
Contact me at patrick.mannion@ubm.com.
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