DesignCon memory preview
Janine Love, Editor, EE Times' Memory Designline -- EDN, January 9, 2012
It's nearly time for DesignCon 2012, and the place to be is the Santa Clara Convention Center January 30-February 2nd. The conference is divided into numerous tracks, which you can check out here. To speed things along, I picked out some memory presentations that I found particularly intriguing (see below for more details). Also noteworthy is the Agilent Education Forum: Design and Test Challenges in Next-Generation High-Speed Serial Standards (PCIe3, DDR3/4, USB 4, FPGA 28 Gbps Serial Link). The forum will include demonstrations on using all of these standards. For more information on this, head here. If you'll be attending the EXPO, you can check out the exhibitor list here.Rambus: Design, analysis, and characterization of 12.8 Gb/s single-ended and 20 Gb/s differential signaling for memory interface
The design and analysis of a 12.8 Gbps/link single-ended and a 20 Gbps differential parallel interfaces using conventional low-cost package and board technologies is presented. The system uses asymmetrical architecture where the equalization and timing adjustment circuits for both memory WRITE and READ are on the controller to reduce the memory cost. We describe the design, modeling and optimization steps employed to mitigate the impact of inter-symbol interference, crosstalk, supply noise on the system margin. The single-ended signaling and the differential signaling achieve reliable communication over a memory channel at 12.8-Gbps and 20 Gbps, respectively. We further present measured data from a prototype systems, implemented in the same silicon technology and sharing many of the critical circuits, under various operating conditions.
Related articles:
- On-chip flash memory reprogramming in single chip mode via an UART interface
- Multi-gigabit data link aggregation for next-generation systems
This session discusses the Power Distribution Network (PDN) design methodology for the DDR4 technology. It also compares the DDR3 PDN methodology with that for the DDR4. Full system PDN is constructed using controller, motherboard, DIMM, and DRAM PDN models. In modeling methodology, distributed modeling for silicon, package and motherboard was used. Frequency domain analysis is performed to determine the resonances in the system, at both ends. Next, the excitation profiles or Icc(t) are generated for different loading conditions, and end to end analysis is performed. There are two modes of operations: WRITE and READ modes. DDR4 has power termination, while DDR3 has center tap termination. The key differences between DDR3 Icc(t) and DDR4 Icc(t) are identified. Transmission lines are used between memory controller and DRAM, so as to capture the PDN current accurately. Also for the READ mode in DDR4, the Icct attenuation will be considered, which provided more accurate simulation.
Related articles:
Memoir Systems: Algorithmic memory: an order of magnitude performance increase for next-generation SOCs
Historically, circuits and advances in lithography have been used at every generation as the approach to enhance memory performance. Unfortunately these approaches alone do not give enough performance improvement, and are not keeping up with applications that require higher memory performance. Therefore, memory performance remains a bottleneck with traditional approaches, leading to the often quoted 'processor memory' gap. This session describes a completely new technique - algorithmic memory, which uses the power of algorithms to make existing embedded memory faster. In particular, algorithms, which are implemented in standard RTL logic, are wrapped around existing embedded memory to expose multiple memory interfaces. These interfaces individually provide true random access memory operations, and can be used independently and in parallel to dramatically increase the total number of memory operations per second (MOPS).
Related articles:
- Startup Memoir Systems makes memory performance programmable
- Minimize failures in memory modules
- Break memory barriers for next-generation servers
For graphics applications, single ended (SE) memory interfaces have experienced a marked increase in data rates. While the need for higher memory bandwidth continues to grow, it is increasingly evident that a multitude of challenges in SE signaling make pushing data rates beyond 6Gb/s exceedingly difficult. It is very essential to be able to isolate, quantify and combat the critical factors that limit the performance of high speed SE systems. A GDDR5 system has been designed using a Rambus test-chip and GDDR5 DRAM. Using simulations and on-chip system level BER testing, factors that affect system performance are identified. Their impact is quantified and solutions to tackle them are evaluated on a system level. A chip-to-chip system between two test chips that mitigates the performance limiters is shown to operate robustly beyond 8Gb/s.
Related Articles: nVidia: Rigorous breakdown of crosstalk in single-ended high-speed memory interface
Single-ended point-to-point signaling speeds are fast approaching 7Gbps and higher in a high-speed memory link. The key to the high-speed signaling strongly depends on the understanding of noise budget of the link - such as random jitter, duty cycle distortion along with its amplification, power supply induced jitter in TX/RX circuitry, and channel deterministic jitter simply referred as ISI and crosstalk. This session particularly focuses on a crosstalk noise with emphasis on a practical point of view. Rigorous crosstalk noise breakdown in a single-ended high-speed memory channel will be discussed in detail followed by analysis of bi-directional crosstalk and the effect of crosstalk phase offset in a link budget. As a result, this session not only shows how to minimize crosstalk noise but also how various forms of crosstalk noise affect a link budget.
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