Stable pulse generator uses matched transistors in a current mirror
Inexpensive dual transistors work as well as do legacy matched pairs.
Bill Morong, Paoli, PA; Edited by Margery Conner and Fran Granville -- EDN, February 2, 2012
Using CMOS gates to generate pulses sometimes causes timing uncertainty due to gate-threshold variations. For accurate pulse widths, you can use BJTs (bipolar-junction transistors). Basing the design on current comparison allows the circuits to operate at low voltages. Proper clamping of the timing capacitor avoids pulse shortening with increased repetition frequency. These circuits work with somewhat less accuracy at supply voltages lower than 5V.
The heart of this design is a current
mirror using modern dual transistors.
Process improvements have made many
ordinary dual transistors inherently
well-matched. Testing a statistically
significant sample of PMBT856 devices
typically yields a better-than-1-mV
match and no mismatches at voltages
greater than 2 mV. As has been true for
decades, PNP-transistor pairs are better
matched than NPN transistors. Testing
PMBT3904 devices yields 2-mV
matches, with none worse than 3 mV. The packages measure approximately 2
mm on a side, which gives good thermal
coupling between the pair. A current
mirror with devices having 2-mV mismatch
has 8% error. Devices with 3-mV
mismatch yield 12% current error. Even
with these errors, the circuit makes
pulses that are more predictable than
those that CMOS devices make.
Figure 1 depicts a simple implementation
of a current-mirror pulse generator.
It provides good performance over a
0 to 100°C temperature range (Figure
2). 
The closely spaced traces in the
waveforms of these circuits are the 0
and 100°C outputs. Source V2 produces
a 40-kHz square wave with a 33% duty cycle. The negative transition of this
wave produces a peak current of 4 mA
in timing capacitor C1. A time constant
of 4.7 μsec is set with the value
of resistor R1. The timing current of C1
and R1 passes through diode-connected transistor Q1, which, being connected
in parallel with the base-emitter junction
of Q2, forms a current mirror that
replicates in Q2 the timing current in
C1 and R1. Because the base-to-emitter-voltage-to-emitter-current curves of Q1
and Q2 match and Q1 and Q2 are at the
same temperature, Q2 current matches
Q1 current. A quiescent current of
about 0.85 mA is set in R3. When the
timing pulse increases Q2’s current to
exceed R3’s quiescent current, Q3 lacks
base current and turns off, initiating a
negative pulse across load resistor R4.When the timing current decays below the quiescent current of R3, base current flows into Q3, turning it on and terminating the pulse on R4. Q2 saturates early in this pulse and becomes less saturated as the timing current decays.
When V2 transitions positive, it drives the bulk of its current into D1, yielding a short recovery time constant. D1 ceases to conduct at one diode drop above V1’s supply voltage, so the recovery tail from that diode drop to the quiescent base voltage of Q1 depends on the current decay in R1, which is a longer time constant. This simple circuit is stable, varying less than 4% over 100°C.
Although stable, this circuit does
not provide high-speed operation. In
the circuit’s quiescent state, there is
no current in either Q1 or Q2, making
for a low gain bandwidth. Also, Q3 is
in saturation, delaying the initial fall
of the pulse across R4 because the free
carriers must leave the base region. Q2
also saturates during the pulse, delaying
the rise at the end of the pulse.
Figure 3 depicts an improved current-mirror pulse generator. In this circuit,
the operation of C1, R1, and D1 follows that of Figure 1. Changing D1 to
a Schottky diode reduces the recovery-tail
voltage that R1 must dissipate. Add
R2 to draw a keep-alive current of 100
μA through Q1 and Q2, speeding turn-on.
These keep-alive currents need
not affect the timing. You can cancel
out their effect with a slight reduction
in the value of R3. Fitting Q2 and
Q4 with Schottky clamps D2 and D3,
respectively, keeps the transistors out
of saturation. These changes improve
high-speed performance
(Figure 4).
Although improved, the circuit still
relies on D1 for the final tail of recovery.
To eliminate this problem, you can
replace D1 with a fourth transistor, Q4
(Figure 5). Because transistors Q1 and
Q2 are slightly conducting, a voltage
one diode drop below that of supply
V1 is always present at their bases. You
filter this voltage with R5 and C2 and
provide it as a bias to the base of Q4.
This step keeps Q4 nearer the threshold
of conduction than would a diode to
supply V1. When source V2 changes
to a negative state, Q4 is fully off and
draws no current. When V2 changes to
a positive state, the emitter of Q4 conducts
at voltages above V1 to catch the
recovery transition, 
further reducing
the recovery-tail amplitude.R6 may be used to limit Q4’s base current, but its omission is acceptable if source V2 has sufficient output resistance. It may be destructive to apply source V2 swings large enough to cause excess reverse voltage across the Q4 base-emitter junction. Q3 and Q4 can share the same package. These additions further improve the pulse generator’s high-speed performance (Figure 6).
Talkback
-
This probably-very useful article suffered from BAD EDITING. Is this truly a pulse generator ? If so, what's that square-wave doing between C1 and ground ? We are forced to guess that this is NOT really a self-contained pulse generator, but instead takes an input square wave and then shortens the pulse or something.
EDN's recent articles have suffered from the lack of a competent editor. We should always get an accurate "black box" description of either what the circuit is doing, or of the "magic trick" in an otherwise uninteresting circuit. I did get some magic because I learned how well-matched are "double transistors", to use NXP's broken English. That's gold for me, but I still wonder if I might want to use that pulse circuit soomewhere.
XSo we need to know (1) what the curciut does - before discussing details (2) the voltage and input impedance of the square wave input. (3) If this is a pulse sharpener, we could use some pointers on what components affect teh timing, beyond C1, and some formula for how C1 and input impedance relate.
Good editing ia like water; you don't miss it until there isn't any. Morong obviously has some interesting things to say, but it got lost in the publishing.
Darrol - 2012-25-2 09:53:47 PST -
Is it April already?
John Bostock - 2012-10-2 01:27:00 PST -
There's nothing modern about using transistors from the same wafer to get better parameter matching--that's been done since before dirt was invented.
The big advantage that monolithic arrays have is thermal coupling. The thermal resistance between two die in a plastic package is only slightly less than that between completely separate packages. For instance, in a SOT143 packaged dual like a BCV61, the thermal resistance between the two devices is over 200 K/W. A 1-kelvin delta-T gives you 2.1 mV of offset, so that much-ballyhooed 1 mV offset only applies for device dissipation less than
Pd_max = (1 mV)/(2.1 mV/K * 200 K/W) = 2.3 mW.
And, of course, that 1 mV of offset corresponds to 4% imbalance in collector current.
Monolithic devices have hundreds of times lower thermal resistance between devices, so you can get far better performance from them.
"Legacy", my Aunt Fanny.
Phil Hobbs - 2012-6-2 18:42:15 PST -
I concur with the others that the actual value of this circuit is a bit hidden. And how inaccurate are those CMOS gates? The gates that get such criticism? Variable threshold will cause some variation in pulse width for some devices from some makers. The solution is often to make the input pulse have faster rise and fall times.
These circuits do represent an interesting set of analysis, though.
William Ketel - 2012-6-2 18:03:06 PST -
I think the title used to read "Monostable Pulse..." Margery? A little help here?
Laserdudephil - 2012-6-2 13:27:20 PST
