The Cadence wide I/O interface not only meets the performance requirements dictated by the Wide I/O memory interface standard in review at JEDEC but also includes unique optimizations such as traffic reordering and low-power features that ensure better overall system operation. Designed to enable maximum system-level performance, the wide I/O memory controller includes advanced algorithms to ensure highly efficient data transfer and to intelligently schedule transactions. The IP has the capability to reorder traffic by monitoring system transactions and delineating between low-priority and system-critical tasks. These unique capabilities enable the IP to maximize bandwidth and minimize latency on critical transactions. The Cadence wide I/O interface also offers additional features, such as “traffic sensing,” which automatically adjusts power consumption based on the type of traffic. The IP has been designed to support operation at multiple frequencies and allows designers to implement advanced power-control techniques, such as dynamic voltage and frequency scaling (DVFS), to reduce power even further. A flexible and configurable design allows the memory controller IP to be custom-fit for each SOC, further reducing time to market and risk.

EnergyCore ECX-1000, Calxeda

ECX-1000 is a complete server on a chip, with four cores of ARM processors, an integrated management engine on a fifth core, a complete suite of I/O controllers and phys, and an 80-Gb crossbar switch that enables seamless scalability up to 4096 nodes. Each EXC-1000 consumes only 3.8W at full utilization. This enables a complete server with 4-GB DRAM to be built that consumes only 5W for a complete server. See more information at www.calxeda.com.

SL1001 universal TV demodulator IC, Saankhya Labs Pvt Ltd

The Saankhya SL1001 is the first universal TV demodulator IC compliant with all worldwide terrestrial and cable, digital, and analog TV standards. The product allows large consumer-electronic OEMs and ODMs to design universal TV chasses. SL1001 supports digital terrestrial standards ATSC, DVB-T, DTMB, and ISDB-T; digital cable standards J.83 A, B, and C; and analog standards NTSC, PAL, and SECAM. SL1001 also supports FM radio, DAB, and DAB++. The SL1001 performance meets test specifications for each standard (A74, Nordig2.0, CESI). SL1001 is based on the innovative Software Defined Radio (SDR) architecture, a fully software-configurable IC, wherein the different standards support is made possible by only the software change. Target applications include HDTV, smart TV, iDTV, analog TV, set-top boxes, TV-tuner modules, PVR and DVR, PC TV tuner cards, TV-tuner USB sticks, tablet PCs, smartphones, car entertainment systems, and digital radios.

Orly multicore STB SOC, STMicroelectronics

Orly delivers more than 8500 DMIPS and features an advanced, energy-efficient multicore ARM Cortex-A9 MPCore processor. It has unique capabilities enabling optimized playback of content and applications through a range of software environments. Orly also renders powerful Adobe Flash-based games, media, and applications that take advantage of an optimized version of Adobe AIR and Flash Player. Dedicated high-performance processing engines deliver outstanding graphics rendering, multimedia experience, and security robustness. Orly also supports the latest broadcast and video compression standards. It introduces enhancements such as dual 1080p 60-Hz decoding, SVC decoding, and HD encoding, which extend the video standards by enabling higher-quality video bit-streaming. Orly also supports full HD 3D at 60 frames/second per eye. This high frame frequency produces unique consecutive images to avoid motion blurring, especially in video games, making the images appear more fluid. Orly extends the graphics experience for HD user interfaces and HD games by integrating a quad-core ARM Mali-400 MP GPU. Combined with Faroudja video enhancement technology, Orly provides video quality comparable to high-end home theater systems.

Zynq-7000 EPP (Extensible Processing Platform), Xilinx

This new class of SOC combines an industry-standard ARM dual-core Cortex-A9 MPCore processing system with an analog-to-digital converter block; high-performance, low-power programmable logic; and 12.5-Gbps transceivers. This processor-centric architecture offers ASIC-like performance and power with the flexibility and scalability of an FPGA and the ease of programmability of a microprocessor. The Zynq family allows designers to target cost-sensitive as well as high-performance applications from a single platform using industry-standard tools. The integration of the ADC block combined with the programmable logic delivers new levels of analog interfacing capabilities, enabling customization for a wide variety of applications. In addition, the Zynq family offers levels of performance that two-chip solutions can’t match due to limited I/O bandwidth and limited power budgets. Ultimately, the Zynq family offers designers a comprehensive platform that enables them to create their own customized SOC that scales from very cost- and power-effective solutions based on the capabilities of the Artix-7 FPGA programmable logic to more comprehensive and performance-oriented solutions on the higher end with devices based on the Kintex-7 programmable logic.

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