Virtual System Platform, Cadence Design Systems

The Cadence Virtual System Platform simplifies the creation and support of virtual prototypes with automated modeling and faster debugging. Design teams can begin developing software weeks to months before a hardware prototype is available, and software teams can use it as their application development platform. The platform is based on SystemC TLM 2.0 and the IEEE 1666 standard, supports third-party processor models and third-party software debuggers, and scales from single-core to multicore software development and debug with performance reaching hundreds of MHz. The Virtual System Platform is a critical piece of the Cadence System Development Suite. Xilinx developed a virtual platform built on Cadence Virtual System Platform (VSP) technology to provide a stable, feature-rich, fast, and functionally accurate model of the Zynq-7000 EPP processor system, its peripherals, memory, and I/O, capable of booting Linux and other operating systems. Complementing this model is the ability for developers to extend the virtual platform using transaction-level models (TLMs) to support custom devices that will ultimately be instantiated within the Zynq-7000 device’s programmable logic. The Virtual System Platform provides an integrated HW/SW debug environment with unique multicore capabilities; it is connected to the RTL verification flow, and automates and accelerates the creation of new TLMs.

MPLAB X IDE (integrated development environment), Microchip Technology Inc

The MPLAB X IDE is Microchip’s next-generation, open-source integrated development environment with cross-platform support for the Linux, Mac OS, and Windows operating systems. Microchip remains the only company to support all of its 800+ 8-, 16-, and 32-bit microcontrollers and digital signal controllers, along with many of its memory ICs, from a single integrated development environment. And the IDE remains a free download. It also provides a single, unified graphical interface for Microchip’s and third-party tools. By adding the option to do embedded development on computers with operating systems other than Windows, Microchip has opened up embedded-design activities in the Mac OS and Linux environments, where support was limited. A host of high-performance features have also been added to the new IDE, including the ability to manage multiple projects and tools with simultaneous debugging, an advanced editor, visual call graphs, and code completion. These added features enable embedded designers to debug their code in new ways that significantly improve their productivity and reduce time to market. The ability to support multiple debuggers is particularly significant, as it allows users to debug a multiprocessor design. Microchip estimates that the MPLAB X IDE’s new features can reduce development times by as much as 40 to 50% when navigating within or understanding code for the repurposing or debugging of a project.

JenNet IP networking solution, NXP Semiconductors NV

JenNet-IP is an IP-based networking solution enabling the Internet of Things for both residential and industrial applications. Using an enhanced 6LoWPAN network layer, it targets ultra-low-power IEEE802.15.4-based wireless networking for residential and industrial applications. Capable of scaling to support large wireless networks with over 500 devices, JenNet-IP has many attractive features, including ultra-low-power consumption, long RF range, low memory footprint, and a low total cost of ownership. JenNet-IP is based on NXP’s proven JenNet network protocol stack, used in over 3,000 installations globally, and runs on NXP’s JN5148 ultra-low-power wireless microcontroller and modules. An elegant and extensible user Management Information Base (MIB) API provides a flexible approach to device management and control, enabling app developers to easily and expediently carry out product development using industry-familiar methodologies. In May 2011, NXP announced its intention to release JenNet-IP network layer software under an open-source license. By supporting an active community of developers and users, NXP aims to simplify the effort required to add "smart" connectivity and two-way communication into a wide range of devices, and help to establish a cross-application standard for wireless connectivity in both residential and industrial environments.

Virtualizer, SynopsysCR-8000

Prototypes created with Virtualizer allow engineers to speed software-development schedules by up to nine months and deliver up to a 5X productivity boost over traditional approaches to software development, hardware/software integration, and system validation. For developers creating a virtual prototype, Virtualizer’s graphical design entry, software debug, and analysis components combined with Synopsys’ broad portfolio of system-level models deliver the fastest time to prototype availability. For software engineers using a virtual prototype of their system to create, integrate, and verify software, Virtualizer Development Kits (VDKs) offer a cost-effective development platform capable of executing unmodified production code at near-real-time speed. VDKs also provide unmatched multicore-aware software debug and analysis capabilities, concurrent hardware/software analysis, and synchronized debugging with third-party software debuggers and integrated development environments. Open and standards-based, Virtualizer supports key industry standards such as OSCI TLM-2.0 and SystemC and runs on both Windows and Linux operating systems. Combined with FPGA-based prototyping, Virtualizer facilitates faster SOC validation and software bring-up at near-real-time performance. Connecting Virtualizer with RTL simulators enables the use of embedded software in hardware-verification environments. Software developers can integrate Virtualizer prototypes with their existing debuggers and IDEs, retaining their existing software tool investment. Virtualizer also gives electronic product developers the ability to conduct system validation by networking multiple virtual prototypes together with physical system simulation, test benches, and virtual I/Os.

Design Force, Zuken

Design Force is a complete system-level IC package and board design and analysis solution that supports single-board, multiboard, and chip-package-board interconnect design. Combining 2D and 3D design in one environment with the latest human-interface techniques, accelerated graphics, and almost instantaneous rendering and refreshing, Design Force is a fast and effective PCB design solution. Menu picks, mouse clicks, and mouse travel distance are greatly reduced, making it much faster and easier to use than comparable ECAD solutions. Using the newest hardware and software technologies, designers can take advantage of fast graphics to place and manage embedded components, view and modify layers, and optimize chip-package-board and multiboard interconnects while moving seamlessly through multiple designs in both 2D and 3D. Multiple client-server implementations are supported, including cloud computing. Design Force has embedded support for high-speed design, allowing engineers and layout designers to conduct signal-integrity, EMC, and power-integrity analysis; manage constraints; and auto route. Improved product quality is achieved by early detection of design errors and verification of performance requirements through the embedded-design analysis and vendor-specific manufacturing rules checking. Designers can effectively co-design a chip, package, and board; embed components in the dielectric; and verify manufacturing rules in real time.

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