Consider a computer system that has a host processor connected to a remote-I/O subsystem (Figure 1). The host clock treats the I/O system, which is located far from the main hardware, as a slave. Because of the transmitters, receivers, remote-system logic, and cable length, the data the host receives has a dramatic latency. This latency can be larger than the clock period. If the length of the cable is indeterminate, then the latency is also indeterminate. The problem with such latency is that receiving registers in the host system might clock in the data from the remote system while some bits are changing. The result is that some data may be corrupt, or, worse, the input registers may go into a metastable state. The circuit in Figure 2 prevents clocking bad or changing data. It does so using only general-purpose, "jellybean" logic. The key is to remote-clock back to host. This action allows XOR gate IC_1A to compare the phase difference between the host clock and the delayed clock.

When the two clocks are nearly in phase, the duty cycle of IC_1A's output is close to 0%. When the two clocks are close to 180° out of phase, the duty cycle approaches 100%. Whatever the duty cycle is, it is constant during normal operation. The only way it can change is for the cable length between the two systems to change. R₁ and C₁ form a lowpass filter. Set R₃ equal to R₄ so that the reference voltage is at midpoint. IC₂ and IC_1B then select whether to clock register IC₃ on the rising or falling edge of the host clock. IC₄ ensures that the data changes consistently with the rest of the host system. Figure 3 shows a (delayed) remote clock that is nearly 360° out of phase with the host clock. If the host were to clock in the data on the rising edge of its clock, metastability would become a concern. You can simply clock in the data on the falling edge of the host clock, but this solution yields the same problem if you choose a new cable with a different length.

Without any analytical effort on the designer's part, the circuit in Figure 2 automatically selects which clock edge to use. Note that comparator IC₂ can be a low-speed part, because it operates at dc only. Note also that if the two clocks are 360±90° out of phase, the circuit uses the falling edge of the clock. If they are 180±90° out of phase, the circuit uses the rising edge. If the R₁C₁ time constant is too low, the resulting ripple can cause the output of the comparator to be unstable. You could use a comparator with hysteresis to reject the ripple. Some instability of the comparator's output is acceptable, because you can safely use either the rising or the falling edge for most latencies. You need stability only when the clock is near 360 and 180° out of phase, so you have little to lose by using a large R₁C₁ time constant to present a dc voltage to the comparator's input.

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