Compiler provides timing closure

The Topomo physical-system compiler from Get2Chip models chip topology while examining the effects of architecture, block size and location, and physical wiring. Topomo integrates and automates block partitioning, block placement, global routing, and synthesis. The tool partitions a multimillion-gate design into system-level blocks based on actual timing and area to achieve convergence. It automatically identifies long and short wires and triggers global synthesis and timing optimization.

You can use the compiler with a number of place-and-route and physical-synthesis tools, including Apollo from Avanti (www.avanticorp.com), Tera-Place from Mentor Graphics (www.mentor.com), and Physical Studio from Sequence Design Systems (www.sequencedesign.com). Input formats include Verilog and Superlog. Prices start at $200,000 for a one-year subscription. It runs on Linux, Solaris, and HP-UX operating systems.

Get2Chip, 1-408-501-9600, www.get2chip.com.