Tool slashes digital-IC test time on existing testers; barely affects fault coverage, die size, or device-design time

If you design or develop tests for complex digital ICs, you should consider Mentor Graphics' TestKompress. The vendor says that the tool cuts device-test times by at least 60% without reducing fault coverage, significantly increasing die sizes, requiring new or different tester resources, or necessitating changes in design methodology. Thus, the product enables the use of existing ATE (automatic-test equipment) to test next year's more complex devices on ATE in less time than that required for testing this year's simpler designs. Moreover, the time required to apply TestKompress to a new IC design is generally only a day or so, and designers become productive with the tool in mere hours. The cost of these benefits—approximately $1 million—may at first seem high, but Mentor's cost models show that most device manufacturers will recoup their investments in months.

The tool uses the suppliers' proprietary EDT (embedded-deterministic-test) technology, which breaks long scan chains into a larger number of shorter chains but scarcely increases the total number of vectors. Although the interface between the tester and the device under test doesn't change, the scan chains execute in parallel using as few as one-tenth the number of clock pulses as they would typically. Scan-test time represents as much as 75% of the time a device spends on a tester, so TestKompress can increase device throughput by more than 68% compared with that of equally complex conventional devices on the same tester. TestKompress uses the same script and automatic-test-program-generation files, test-vector formats, and tester interfaces as Mentor's Fast-Scan test-insertion tool, which is necessary for running TestKompress.

Mentor Graphics Corp, 1-503-685-7000, www.mentor.com/dft.