FROM EDN EUROPE: Programmable analogue ICs challenge Spice-and-breadboard designs

It's 1978, and your design landscape is about to change. Microprocessors have been available for several years, and there's a good chance that you've tried a 6800 or 8080. But for general digital-system design, you still rely on drawers full of TTL or CMOS chips that future designers will reserve for glue-logic functions. Then Monolithic Memories introduces the first PLD (programmable-logic device). It mops up small- and medium-scale integration functions and—better yet—lets you reconfigure circuitry without a pc-board redesign.

If you're a digital designer today, that first PLD looks tame compared with contemporary products. But if you're an analogue designer, it's still highly likely that you rely on the same techniques that you used in 1978. Recent device introductions challenge such anachronistic approaches and provide software tools that make analogue design approachable for digital engineers.

With integration beyond commodity-IC level limited to high-volume custom ICs, the case for programmable analogue is particularly strong. Accordingly, several vendors have been involved in the race to market, with Zetex producing the first field-programmable analogue device in 1996. Fast Analog Solutions, a Zetex subsidiary, calls its device a TRAC (totally reconfigurable analogue circuit). TRACs are largely the result of academic work by Professor David Grundy, an academic and independent consultant who champions a structured computational approach to analogue design. Other programmable analogue building blocks are available from Anadigm and Lattice Semiconductor. Anadigm is a start-up whose FPAA (field-programmable-analogue-array) technology descends from original research at the now-defunct Pilkington Microelectronics. Motorola purchased the technology in 1997 and launched its MPA1000 family of reconfigurable devices only to withdraw from the market following a restructuring of its semiconductor business. Anadigm—founded by CEO Mike Kay, sales and marketing director Ludwig Klingenbeck, and technical director and ex-Pilkington employee Ian Macbeth—rose from the ashes. By contrast, digital PLD expert Lattice Semiconductor needs no introduction. Its recent entry into programmable analogue products marks a new venture for the company and stresses the growing significance of this business sector. Programmable analogue ICs will soon be a commodity item.

Although the process technologies that vendors employ are proprietary, you can classify FPAD (field-programmable-analogue-device) products as linear (continuous-time) or switched-capacitor designs. Each design has its trade-offs that, in practice, reduce to balances among application simplicity, device resource usage, and flexibility. Continuous-time circuits are the traditional linear models, and, because they avoid artifacts due to sampling processes, they require less consideration for filtering. Such circuits are also easy to build (in terms of process technology) and provide predictable performance across their full bandwidth, without spurious switching artifacts to complicate response. But the downside to the purely linear approach is that the circuit elements for any configuration are fixed. For example, there's no way to control an individual resistor value in a feedback loop. Depending on how the device implements its circuit blocks, you may need a multiplier to implement a programmable gain amplifier. Classic op-amp multiplier circuits require signal and multiplicand inputs that, particularly for higher quadrant counts, can consume multiple device cells and I/O pins.

To provide greater flexibility and reduce resource consumption, switched-capacitor topologies replace fixed resistors with capacitors and control switches (Figure 1). To a first approximation, the charge that transfers from node 1 to 2 depends on the capacitor's value and the switching duty cycle, synthesising a linear variable resistor. Although the idea is simple, challenging IC-design techniques and process technologies are necessary to overcome noise and nonlinearities due to phenomena such as charge leakage and voltage variations across the switch's full duty cycle. But companies such as Linear Technology have been successfully producing switched-capacitor ICs for several years for applications such as programmable filter circuits. However, the switching action generates a sampled-data system and its attendant characteristics, such as the Nyquist limit and spectral-response considerations familiar when you apply ADCs.

Another minor architectural difference between today's FPADs concerns the signal routing topology. Grundy's analysis promotes what he terms a stringlike chain of analogue-signal-processing elements that decomposes functions into serially connected circuit blocks (Reference 1). This architecture is clearest in the TRAC design but applies equally to the other products. The difference is that TRAC relies on serially connected cells. You either connect the cells directly, one to the next, or you insert a noninverting pass element to bridge across cell locations. If you want to arbitrarily route a signal elsewhere in the array, you must insert a high-impedance cell to facilitate I/O connections. The other products avoid sacrificing cells for I/O by including a routing pool of varying complexity. These differences become clearer as you evaluate each vendor's freely downloadable design software. The vendor's design software also provides a graphical insight into all device resources.

Fast Analog Solutions uses classic linear circuitry in its 20-cell TRAC020LH, which is built in a BiCMOS process. The array is organised as two vertically aligned rows of 10 horizontal cells together with their I/O pins (Figure 2). The device's noninverting small-signal performance is virtually flat to 1 MHz and usefully extends to about 5 MHz. The IC requires a 5V power supply and refers its analogue ground level to nominally 2V. The input-signal range is then ±1V with respect to analogue ground, and the digital signals span the normal 0 to 5V range. Input impedance depends upon the function you select but is typically 60 MΩ for a noninverting amplifier and 40 kΩ for the IC's computational functions. Cells can sink and source around 150 µA, so you'll almost certainly need external buffers to drive loads such as ADCs. THD performance with a 1V p-p input signal typically measures 0.08%, falling to 0.02% with a 100-mV signal. Dynamic range is typically 80 dB, and noise voltage is 15 nV/ within a 10-Hz to 100-kHz bandwidth.

TRACs' in-system programming arrangements rely on a common clock and daisy-chain serial communications that you can cascade between multiple devices. Alternatively, if you need the same design in multiple devices, you can simply connect the data-in pins. At power-up, a microcontroller can configure the device, or logic can download set-up data from a serial ROM, exactly as for an FPGA. A dedicated IC, the TRAC-S2Q16, is available to control a serial memory and to provide optimum load/store timing. Internally, each TRAC cell includes a serially programmed 3-bit configuration register that selects one of eight cell configurations:

• add, for an inverting summing amplifier with unity gain;
• negate, for a unity-gain inverting amplifier;
• noninverting pass, which you use for serial signal routing;
• log, for a logarithmic amplifier;
• antilog, for an exponentiation amplifier;
• rectifier, for a precision rectifier with an exponential response;
• aux, or auxiliary, for external component connections; and
• off, which you use to set a cell's I/O as high-impedance.

These few configurations provide the basis for virtually any analogue design. The most prominent building blocks that are missing from the on-chip implementations are integrators and differentiators, both of which are easy to construct using the chip's "aux" external-component mode. Thus, the TRAC concept resembles an analogue computer with emphasis on log/antilog techniques for multiplication. The TRAC020LH is available in a 36-pin QSOP and costs $8.50 (1000); the supporting TRAC-S2Q16 is a 16-pin QSOP and costs $1.70 (1000).

Constructed from E²CMOS, the Lattice ispPAC10 and ispPAC20 ICs also use a purely linear architecture. Running from one 5V supply, the PAC10 accommodates four programmable analogue macrocells (or PACblocks), and the PAC20 houses two macrocells, two comparators, and an 8-bit DAC that you can use to set the comparators' threshold levels. Each macrocell includes three programmable cells that comprise a pair of instrumentation amplifiers at the inputs, followed by a summing/output amplifier combination (Figure 3). You can program the input amplifiers for gains of –10 to +10 in unity steps. The feedback loop around the sum-and-output amplifier block includes a capacitor array and dc-feedback paths. The dc response is fixed at unity gain, but you can open-circuit the resistive path, leaving a feedback capacitance that you can program from 1 to 62 pF. These characteristics target ispPAC devices toward signal-filtering and processing duties, typically ahead of an ADC. (A third family member, the ispPAC80, is a dedicated filter chip.)

To optimise parameters such as common-mode rejection and signal-to-noise performance, ispPAC's signal paths are fully differential. Compared with single-ended operation, this approach effectively doubles dynamic range and constrains unity-gain offset-voltage contri-

butions to 1 mV. You can configure single-ended inputs by biasing one of the differential inputs from the chip's reference-voltage output. The voltage reference generates a 2.5V level that is used to centre signal levels and act as a virtual analogue ground. This voltage level permits the device to handle I/O voltage swings of as much as 4V from one 5V supply; it's is also compatible with common ADCs, which the 10-mA rated output amplifiers can drive directly. Other key performance characteristics include a unity-gain bandwidth of 550 kHz that falls to 330 kHz at a cell's maximum gain of times 10. Input-referred noise-voltage performance at maximum gain is less than 40 nV/ from about 2.5 kHz upward, but low-frequency noise performance rises to about 400 nV/ at the 10-Hz point—a characteristic of CMOS fabrication. The ispPAC10 and PAC20 each cost around $7 (1000) and are available in a 28-pin DIP/SOIC and a 44-pin PLCC, respectively.

Anadigm's 10E40 FPAA employs a switched-capacitor technology that's currently built in 0.6-micron BiCMOS. Like the Lattice parts, the FPAA runs from a 5V supply and generates a virtual analogue ground at 2.5V; the input-voltage swing is then ±2V relative to analogue ground. The heart of the device is a 20-cell array of CABs (configurable analogue blocks) arranged in a four-by-five matrix. Each cell comprises an op-amp surrounded by a capacitor-feedback network and signal-routing resources (Figure 4). The FPAA surrounds this functional array with 13 configurable I/O buffers that have a typical input offset voltage of 2 mV and –3-dB bandwidth of 10.8 MHz. These buffers drive a 1-kΩ/100-pF load and route signals on and off chip. The array's analogue-performance characteristics include frequency response of dc to 100 kHz with ±0.02-dB flatness, THD of typically less than 0.02%, and voltage noise of 4 nV/ within a 100-Hz to 500-kHz bandwidth.

Other chip resources include an 8-bit programmable reference-voltage generator, four programmable clock dividers, and two uncommitted op amps. The programmable voltage-reference generator provides a globally available internal level that's useful for tasks such as setting a comparator's threshold level. Because the chip's capacitor-bank values are fixed, the clock dividers accommodate circuit blocks with different frequency-response characteristics by providing alternative frequencies to clock the device's switches. The recommended master clock frequency is 1 MHz, which, for example, lets you design a lowpass filter with a programmable corner frequency of 400 Hz to 100 kHz, Q of 0.1 to 1.5, and passband gain of 0.01 to 20. The uncommitted op amps let you implement circuits using external components. You can also add components around the I/O buffers, typically to construct antialiasing filters ahead of an ADC.

You configure cells by selecting from a library of "IPmodules" that currently comprises more than 50 circuit functions. These functions range from simple comparators and programmable-gain amplifiers to complex circuits, such as a sine-wave oscillator and various biquadratic filters. An SRAM block holds the FPAA's configuration data, and its configuration logic supports two modes of operation that depend on the state of a mode pin at power-up. If the mode pin is low, the FPAA loads configuration data from a serial ROM; if it's high, the chip sets itself into microprocessor-interface mode and downloads configuration data from a host's memory space. Serial ROM mode works as for a normal FPGA, but microprocessor mode provides the greatest versatility by supporting reconfiguration on the fly. Dynamic reconfiguration takes about 100-µsec, which is fast enough to suit applications such as adaptive signal conditioning in the front-end of a data-acquisition system. The AN10E40 comes in an 80-pin PQFP and costs $14.50 (10,000).

Facts and figures can't represent ease of use, so how user-friendly are these devices, and how well do they perform? To answer these questions, each vendor provided EDN Europe with a development system. Space constraints deny a blow-by-blow analysis and limit initial checks to a simple amplifier configuration but still provide an insight as to what's available.

The Lattice ispPAC10 comprises a small board that houses one device, a breadboard area, four BNCs, and various headers and jumpers. A download cable plugs into a PC's parallel port to program the board. The board requires an external 5V supply to its two banana sockets; static consumption measures approximately 20 mA. For ease of use with grounded test equipment, this supply should be floating. System software comes on a CD together with the user handbook, various datasheets, and application notes; hardcopies are also available. The company also provides you with a spare device to try. The user manual enables you to develop a working design within an hour of unpacking the box—especially if you use one of the library examples. There are 12 such examples, seven of which suit the ispPAC-10 and illustrate various gain, filter, and signal-summation combinations. Modifying the gain-of-20 example for unity gain is a good starting point; you simply select the device symbol and pick new parameters from a drop-down list. The library example achieves 20× gain by summing two 10× inputs. You can use a similar parallel arrangement, cascade stages to create responses beyond the ±10 gain that each input amplifier supports, or do both.

A software simulator includes a dialogue box to establish start and stop frequencies, a number of points per decade to calculate, and the I/O nodes for testing. The simulator then simultaneously displays as many as four I/O combinations. Each of these paths has a toolbar button so you can, for example, compare iterative results from design changes for one channel. You can also get a direct readout of gain and phase magnitude by positioning a crosshair on a trace. You download the configuration file—which takes about 100 msec—and verify it from the Tools menu. You can also upload devices, so if you create a new design and run Upload, your design appears in a new window.

BNCs make connecting a signal generator and scope easy; you route the connectors to the device's I/O pins using jumpers. If you leave the inputs in their default differential state, you need to offset your test signal by around 2.5V. For a unity-gain configuration and with 2V p-p input signal, you should see a pair of 1V antiphase signals at the output connectors, offset from one another by 2V. Sweeping a test signal from 10 Hz upward reveals that the device's –3-dB point lies at approximately 550 kHz. This result exactly reflects the data-sheet promise, and the simulator predicts –2.66 dB. A quick check for spectral purity with a 10-kHz sine-wave input shows all artifacts lying below –65 dB, almost equaling the arbitrary waveform generator that provided the stimulus. These results don't represent a calibration lab set-up and reflect what you might expect with a quick benchtest. Thus, if you measure results that are significantly beyond expectation, don't immediately blame the chip; check your measurement setup. The ispPAC Designer evaluation products cost $149 and are available now.

The TRAC system is considerably more complex than ispPAC, but the CD's beta version 4 software installs easily. The development board houses four devices and support circuitry, including a 5V supply, and connects to a PC's parallel port. An ac adapter provides raw dc power. The system comes with a bag of jumpers that you can use to route signals among the devices, courtesy of a carefully considered connector array. A user guide and a device data sheet make up the paper documentation. The software's TRAC Manager facility verifies that the board is working and also reads back the contents of installed devices. The sample library contains 18 design examples, including half-and full-wave rectifiers, a four-quadrant multiplier, a programmable filter, and a voltage-controlled oscillator. The half-wave rectifier is the simplest and is a suitable starting point. Consuming two cells, this example demonstrates one of TRAC's idiosyncrasies in that the logarithmic function must precede the rectifier. Because the rectifier uses a modified antilog function, the log function is necessary to maintain linear response.

The eight TRAC functions appear on a floating toolbar that allows you to drag-and-drop your selection into a cell. The Link Manager tool permits connections between arbitrary cells, rather than the normal serial string. As an aid to documentation, you can add textual descriptions to cells and I/O pins that subsequently appear if you leave the cursor over them for a short time. Colour coding helps identify device I/O pins, and right-clicking on a pin toggles the scope function that's part of the software simulator. The simulator provides virtual signal sources that you map to device input pins. (This function produced a Visual Basic script error but nevertheless seems to work.) The default signal is a sine wave, but you can also select square, triangle, saw-tooth, ramp, ripple, and pulse shapes. You then have the usual controls for amplitude and frequency plus less usual offset-voltage and phase-offset controls. Simulation results appear as a graph and are available as printable text files of result point calculations.

A unity-gain amplifier is easy to configure; you select the NIP (noninverting-pass) configuration, which is typically used for internal signal routing. When you're ready to test your design, download the design file to the board using the Send Configuration tool. You can read the device contents back with TRAC Manager, which opens a new window and provides confidence that all is well. Optionally, you can download configuration data to an EEPROM on the board; a read-back facility is also available. The software eases evaluation board hookup by including a component visualiser that identifies I/O positions within the board's connector array. For a 2V p-p sine-wave input offset to match the system's 2V level, measurements show a virtually flat frequency response (typically less than or equal to –0.5%) from 10 Hz to 10 MHz. A spectrum-analyser check with a 1-kHz input signal shows 50-Hz energy around –60 dB. (That level should improve in target systems with good grounding.) Inexplicably, spurious signal peaks of a similar level appear at about 68 kHz, decaying in harmonic multiples to about 550 kHz. Interestingly, there were traces of 68 and 136 kHz in the signal-generator output in this configuration but nothing above this frequency. The TRAC development system is available now for $430.

Anadigm's development board comes in a circular format the size of a CD. The board accommodates one FPAA device, a 68HC908 microcontroller, serial ROM socket, RS-232 interface, and a 5V regulator. Documentation consists of a manual that describes FPAA data, applications information that includes the board's circuit diagrams (other vendors take note), and descriptions of the preconfigured IPmodule functions. The system communicates using the host PC's serial port. The board also includes an SPI and connections for external logic to drive the FPAA that are useful when you want to try target-level communications. Headers that connect to every FPAA pin make it easy to monitor nodes and add external circuitry. Four switches load the FPAA with configuration data from the microprocessor's flash memory, where you can store your own setups. This feature helps ensure repeatable test setups and allows you to use the board without a host PC to quieten measurements. Two 3.5-mm stereo line sockets serve as analogue I/O ports, and various jumpers set the board's hardware configuration.

The configuration software enables you to drag and drop IPmodules into place. Further configuration includes right-clicking on a module to adjust its parameters in a pop-up window. Most of the more than 50 functions consume one cell, and none takes more than three. (If you require more filter functions than the standard library provides, you can download the companion FilterDesigner software for free.) The interactive Wire tool lets you connect between cells and I/O buffers using local routing resources that display as rubber-band lines between valid routes. Adding to the normal repertoire of signals such as sine, square, and triangle, the simulator includes the ability to construct an arbitrary waveform (Figure 5). You can import data in a numerical text-file format, such as many digital-storage scopes produce. The software also processes Windows' pulse-code-modulation .wav files, so you can generate and process audio samples within the Windows environment.

The board comes with four preconfigured demonstration programs stored in the host micro's flash memory. One example configures the FPAA as a noninverting amplifier for initial parametric checks. Again, you must offset the input signal by the 2.5V analogue ground level. Alternatively, you can ac-couple the input signal; response checks reveal that gain error is –1.19% at 10 Hz, where ac coupling roll-off effects dominate. Response is typically –0.85% through mid-band frequencies and measures –0.5% at 100 kHz, which is today's upper limit for filters in the IPmodule library. It's important to note that the FPAA on this ex-demo board is preproduction silicon; today's production silicon is flat to within ±0.02 dB. Maximum output signal before clipping measures 4.6V p-p, and the I/O-buffer-offset voltages average 2 to 3 mV.

Because it's a sampling system, you might expect the maximum bandwidth to be the Nyquist limit at half the 1-MHz clock frequency. Sine-wave responses show the onset of sampling effects at about 200 kHz, but there's no noticeable roll-off at 500 kHz. The spectrum of a 1-kHz sine wave shows clear traces of the signal's image frequencies at the FPAA's output. Here, too, there's considerable measurement noise from the test environment that appears as 100-Hz peaks. These mains-frequency artifacts beat with both the signal and sampling frequencies to generate wideband noise. Configuring an I/O buffer as a second-order filter using two capacitors and two resistors removes mains-frequency noise from the measurement to highlight spurious harmonic responses. Such a filter rolls off response at 40 dB/decade and prevents sample-frequency noise from mixing down to lower frequencies. The FPAA's dominant noise contribution appears then at multiples of the signal frequency, with a peak of around –45 dB at the sample clock frequency; its random noise floor is typically less than –100 dB (Figure 6). The AN10DS40 development board is available now for $499.