From EDN Europe: Convert large PLD designs to mask-programmed form

If your design incorporates a large programmable-logic device, and part of the plan for the project includes the option to move to an ASIC when and if the product reaches volume production, you may be wrestling with the task of making that conversion. How do you balance the extra NRE (nonrecurring-engineering) charges for generating the ASIC form of the chip against the lower cost per device? Are you better using engineering time to make the conversion and reduce the costs of the product now in the market or using that scarce resource to develop a new generation or new product?

Altera aims its HardCopy at solving this dilemma. HardCopy devices are some of Altera's largest programmable devices, lacking all the circuitry they need to make them programmable and including a metal- (mask)-programming alternative. This combination yields a device that is, for the same gate capacity, 70% smaller in silicon area. The resulting device is more cost-competitive with an ASIC.

Using your programming files and any other data, such as test vectors, for a working device that you have designed in its programmable form, Altera guarantees that, for $100,000 to $200,000, it will produce in about seven weeks a prototype mask-programmed, pin-for-pin-compatible version. (The process assumes that you have successfully implemented your design in a PLD.) Altera stocks uncommitted silicon of the equivalents to its programmable parts and has to generate only the metal layers. The company envisages that this approach will be worthwhile for designs of approximately 400,000 or more gates and for volumes of 2500 devices or more. Price per device will be as much as 80% less than the programmable equivalent.

Altera emphasises that this process is not an ASIC conversion; you get the same logic elements and other structures that you have been working with on the programmable device but in mask-programmed form. However, the process generates a new device routing, because the HardCopy chip replaces the existing route structure. Altera also adds logic to enable test and other functions, but this addition is transparent to a designer. As a smaller die, the HardCopy device is intrinsically faster. The conversion usually hides this speed increase, but you can make a device faster after conversion than you can in the programmable form. The overall objective, Altera says, is for the customer to have minimal engineering involvement in the conversion. The first products to be available in HardCopy form will be Apex series devices, such as the largest EP20K1500E chip; Apex II and Excalibur series parts will follow in 2002 (Picture).

Altera, +44 1494 602000, www.altera.com.