From EDN Europe: Define your own instructions for network processing

With Version 1.2 of Silaria's proprietary tool chain, you can configure the scalable protocol processor Proteus3 to any bit width from 4 to 256 bits. You can also tailor all the elements of a RISC processor, including instruction set, type and number of registers, interrupts, and memory interfaces, to suit your needs. IP (intellectual-property) vendor Silaria focuses on providing configurable-processor cores for network-processing functions.

Because some functions are processor-intensive when using a conventional microprocessor, Silaria's IP and tool set relieves bottlenecks by either providing the means to directly execute these functions or allowing the designer to create the necessary resources. With the tool chain, you can generate user-specified instructions that are implemented in hardware and automatically supported in a C/C++ compiler and in a cycle-accurate simulator. Proteus3 supports instruction widths of 8, 16, 24, and 32 bits; the 8-, 16- and 24-bit variants are compressed forms of the most commonly used 32-bit types. This feature combines with the efficiency of the user-generated instructions to support claims of very high code density. The system outputs the hardware you define as standard HDL for implementation via any conventional ASIC or FPGA tool chain. (The company promises support for SystemC at a later date.) With extensive clock-tree gating, power demand is less than 0.2 mW/MHz for a 32-bit core in 0.18-micron CMOS running at 1.8V.

Silaria, +353 1 8733 145, www.silaria.com.