The smaller the geometries, the larger the problem

Moore's Law is a fundamental and often-cited law in the semiconductor industry. It predicts that the number of transistors per centimeter squared doubles every 18 months, resulting in a CAGR (compound annual growth rate) of 59% in available transistors on a die. The law has held for almost 30 years, during which time it has generated two major methodology changes. The first one occurred in the late 1980s, when the number of available transistors became too large for manual layout. Hardware-description languages and synthesis replaced schematic editors and manual tape-outs. The second change is happening now, as issues with parasitic effects are presenting a new discontinuity.

Until about two years ago, digital designers had to know only logic design to produce bigger and faster products. Yet the ability to develop and manage larger designs did not grow as fast as the ability to manufacture them. Designers' productivity has improved at a CAGR of only 20 to 25% during that time (Figure 1). The capabilities of semiconductor foundries and the abilities of designers have been increasingly diverging, creating the often-talked-about "design-productivity gap." But when foundries became able to fabricate devices with feature sizes of less than 0.20 microns, chip designers faced a new set of challenges. It is now possible to produce chips using 0.18-, 0.13-, and 0.10-micron features, depending on the designers' needs and the capabilities of the chosen foundry.

The methodology for designing digital logic based only on functions, synthesizing the circuit, and handing it over to place and route no longer yields functioning devices. A new methodology is required that means not only new EDA tools but also retraining of logic designers, who, for the most part, have had little formal training in physics and electrical design. There used to be a significant difference between logic designers and IC designers; IC designers would take the netlist from the logic designers and perform the place-and-route functions.

The requirements of deep-submicron design, as the world below 0.20 microns is called, demand that logic designers become proficient in many of the techniques that IC designers use. Market pressures compound the problem, because engineers must learn on the job while striving to meet ever-shrinking development schedules with smaller budgets. Project complexity also challenges engineering managers with new problems for which they have, in general, received no training. EDA companies have responded by introducing a new generation of tools, mostly targeting analyzing and fixing problems they encounter in the place-and-route phase of development. Designers must learn to use the tools and, more important, to avoid the causes of some of the problems during design and development.

As device features become smaller, more gates are available per die, enabling bigger designs. The relative size and proximity of the features become more and more important, until the characteristics of the operating environment surrounding a transistor or a trace become as relevant as—and sometimes more relevant than—its intrinsic characteristics. In addition, engineers had always been able to consider a connection between two gates as a passive conduit that transported information. Now, traces are active devices with physical behaviors that interfere with the orderly transmission of information. At processes greater than 0.20 microns, gates were almost always bigger than connections, and the operating frequencies were generally too low to generate significant physical problems. Of course, the appearance of new problems has not been sudden, specifically limited to deep-submicron-process technologies. Companies pushing the capabilities of silicon to its limits began to encounter analog issues with digital designs at 0.35 microns. By the time the process reached 0.25 microns, it became evident that new EDA tools would be necessary to implement the next generation of electronic products. The alternative would have been a stagnant worldwide economy.

Most of the problems facing designers of deep-submicron designs are interconnect-centric. An interconnect is the trace that connects the output of a gate with an input of its logical follower gate, or an output pin. Engineers working in deep-submicron processes must consider issues with power distribution, signal integrity, electromigration, and manufacturing technology.

Timing closure is the problem most generally associated with deep-submicron designs. Timing closure has always been a requirement of IC design, and until the arrival of deep-submicron processes, designers achieved this closure using statistical wire-load models. The approximate values this method derives are accurate enough, because the wire delays are a relatively small portion of the total delay. In deep-submicron designs, wire delays constitute the larger portion of the total delay, and power- and clock-distribution and signal-integrity issues contribute significantly to the total delay value.

Signal integrity dominates much of the discussion because it directly impacts timing closure. Figure 2 gives an idea of the variety of effects that you must take into account during signal-integrity analysis. Some signal-integrity effects can be static, so you can define a number of design constraints before synthesis. But other effects are dynamic and result from the behavior of signals on adjacent traces. In this case, designers must be able to count on a reliable feedback loop from the place-and-route step back to the logic design to refine the constraints given to the logic-synthesis tool. Accurate modeling of cell libraries has been the key to success since the introduction of synthesis. Before deep-submicron design, the models were static, because greater accuracy was unnecessary. Gate delays constituted the biggest portion of design delay, so an accurate cell library guaranteed accurate timing-analysis results. A model of an interconnect cannot be static, because interconnects come in all shapes and sizes to meet layout requirements. Designers must express the values for electrical and physical characteristics for each interconnect in the form of functions, and traditional cell-library formats can support only constant values The ALF (Advanced Library Format) standard, developed under the auspices of Accellera, provides this capability.

The parasitic values associated with an interconnect are a function not only of its size and shape, but also of its immediate environment. The characteristics and behavior of traces near the trace in question can cause coupling capacitance, which produces signal-integrity issues when signals fail to switch, switch unexpectedly, or fail to arrive on time. Voltage drop (also known as IR drop) has also become an issue, because designers tend to use the smallest amount of power possible. Relative line resistance increases, and power margins decrease, resulting in possible timing failures. As line widths decrease, electromigration also becomes an issue, particularly for high-speed designs. The thickness of the deposition layer necessary to manufacture a trace can be greater than the width of the trace. In this case, antenna effects are possible, spreading EMI throughout the device. Noise modeling also still requires improvement. Noise presents various challenges. Most of the factors that make deep-submicron design challenging contribute to noise. But noise is also the result of signal behavior, so an accurate model requires extensive verification to prove that noise levels are within tolerance.

Spice limitations are a major obstacle to achieving accurate modeling of electrical effects in deep-submicron designs. Despite being more than 20 years old, Spice remains the most popular tool available to model electrical behavior at the transistor level. The complexities of deep-submicron design are taxing its matrix-solver algorithms, so that either the solution does not converge or the execution time is so long, it's unrealistic. The physical issues of different geometries mean that you can no longer ignore many items. Thinner gate materials, for example, mean that EDA tools must solve hot-carrier-injection and negative-bias-temperature instability problems, especially for high-speed designs. Design engineers continue to show creativity; they are able to generate results that are within tolerance by relaxing some of the parameters. Celestry has developed UltraSim, a transistor-based simulator that provides Spice-accurate results in a reasonable amount of time and with computational capabilities to address deep-submicron issues.

All of the companies mentioned this article—whether EDA vendors, systems houses, or semiconductor manufacturers—stress the importance of a team approach. Sun Microsystems, for example, invests significant resources working with EDA vendors to establish methodology requirements and to tune models that analysis tools need. It also diligently qualifies its semiconductors partners. Sun believes that the handoff should be at the gate-level netlist, so that the manufacturer can own both the final place and route as well as the preparation for manufacturing. This concept is important because it gives the authority and the responsibility to the party who has the most control over the final phase of development. Given that the feature sizes in deep-submicron design—especially at or at less than 0.13 microns—are smaller than the lithography wavelength, optical-correction and phase-shifting techniques, such as those that Mentor's Calibre product supports, compensate for the "out-of-focus" effect that would otherwise result. Therefore, it makes sense for manufacturers to handle final placement and routing, the generation of the masks, and their verification; all these functions directly impact the final silicon.

The best way to address a big problem is to break it down into more manageable components, which you may break down even further. This method is the foundation of hierarchical design. Engineers have been using hierarchical logic design for as long as logical synthesis as been available, so logic designers are well versed in its application. Its evolution consisted mostly in the EDA tools' ability to handle bigger and bigger blocks until engineers recognized the possibility of reusing portions of designs by turning them into specific functional blocks of logic. The demands of deep-submicron design impose additional restrictions and requirements on the methodology. You must now consider issues such as signal integrity and power distribution when partitioning a design into blocks, because trying to fix potential problems after synthesis is too time-consuming and, at times, impossible without a total redesign. Thus, it is too expensive. You must plan interconnect and power-distribution strategies before synthesis (see sidebar "Constructing hierarchical power networks for nanometer chips").

Even the most well-planned designs are not guaranteed to be problem-free, so you must develop a robust feedback loop that ensures that you can transmit information about problems identified after synthesis to the front-end tools with integrity. A new family of tools extracts constraints from postsynthesis placement. Designers use the extracted values to achieve timing closure. Cadence, Magma Design, Monterey Design Systems, and Synopsys provide products that allow logic designers to consider signal-integrity issues during logic design.

Synopsys has long dominated the synthesis market with Design Compiler, a logic-synthesis product. But the company realizes that the new deep-submicron issues are beyond the capabilities of Design Compiler and has wisely planned its replacement: Physical Compiler. Physical Compiler deals with signal-integrity problems by combining logical synthesis with signal-integrity analysis and placement. Combined with Chip Architect, Clock Tree Compiler, and Route Compiler, Physical Compiler provides a methodology that in mid-2002 will support the design, synthesis, and placement and routing of deep-submicron products.

Magma Design recognizes that timing closure is a function of avoiding signal-integrity problems due to the proximity of long wires, signal directions among nearby wires, and slew rates. Its approach is to fix the timing on signal paths and change the layout to accommodate the timing, given the constraints that the designer defines. Therefore, the characteristics of a route remain constant even if its topography changes. Cadence has integrated the synthesis technology it acquired some years ago with analysis tools to produce PKS (Physical Knowledgeable Synthesis), which provides a flow similar to that of Synopsys' product. Monterey Design Systems offers front-end planning tools and back-end analysis tools. Its products work with logic-synthesis tools from Synopsys, Cadence, and Synplicity.

Once engineers achieve timing closure and correct logic functions at the gate level, they need to finalize the chip layout. Synopsys will release its Route Compiler for general distribution in mid- 2002, but Avanti and Cadence currently dominate the market. Cadence has had the longest presence in this market, and all of the flows described above integrate with the Cadence place-and-route tools. Avanti has experienced significant self-inflicted business trouble. Although the company lacks a synthesis product, its back-end tools are competitive. Designers use front-end products from Synopsys, Magma, or Monterey to obtain a gate-level netlist that engineers can input into Avanti's products to produce the final chip layout.

Get2Chip introduced Topomo, which aims to provide system-level timing closure with topology modeling. In most cases, engineers synthesize blocks and then stitch them together to form the system. Topomo allows interactive chip planning and refinement by computing and displaying slack distribution, performing global routing to extract interblock capacitance, and resynthesizing logic to meet global-interconnect timing requirements. The tool also allows designers to plan power distribution at the architectural level. By optimizing data paths, logic sharing, registering inputs, sharing registers, and gating clocks, engineers can considerably diminish the chip's power requirements.

Once you establish the new architecture, you can synthesize it with a much higher expectation of success. It is always easier and cheaper to avoid a problem than to try later to fix one, especially if it does not surface until after final routing. NEC shares Get2Chip's point of view on this subject. NEC has seen that most designs begun in the last six months target processes smaller than 0.20 microns and is convinced that a new design flow is necessary to address the size of today's designs and those forecast for the immediate future. Hierarchical partitioning influences the physical characteristics of the chip, and engineers must be aware of the impact of partitioning on silicon.

A variation of this methodology is based on the observation that purely hierarchical systems have a limit on the size of the blocks they support. Therefore, engineers are constrained both in what they can implement in a block and in being able to consider the entire design when making trade-offs or establishing constraints. Digital deep-submicron designs are large, with average sizes easily exceeding 10 million transistors. The databases for such designs are also large, and traditional methods require a 64-bit workstation to handle the design. Sequence Design provides a persistent view of the electrical characteristics; the company can handle a flattened view of a design, even in a 32-bit machine. The advantage is that customers can execute Sequence's products at considerable savings using an Intel-based (www.intel.com) workstation running Linux. Of course, Sequence does not provide an entire suite of tools, so customers still need to have 64-bit workstations. But they need fewer of them.

Sequence's PowerTheater provides power analysis at the RTL (register-transfer level) and allows engineers to define power islands to minimize total power consumption. Having defined functional areas that require different power or power at different times during execution, engineers can design various power rails for those areas. By identifying paths that are not timing-sensitive, engineers can also lower the chip's power consumption. Focusing on lower power consumption potentially saves chip area and may lower noise. PhysicalStudio deals with signal-integrity and timing issues at the chip, block, and gate level, and ExtractionStage analyzes gates, wires, and transistors for timing, signal-integrity, and power violations. The tool suite allows optimization after placement and before and after routing, and it provides designers with a way to deal with both net-to-net capacitance and trace inductance, especially with high-speed designs.

Many deep-submicron chips use copper as their conductive metal. Copper has low resistivity, so its inductance has a greater impact on signal quality than that of other metals. Sequence does not have its own synthesis or routing products, so its tools integrate with products from Avanti, Cadence, and Plato. The integration with Plato tools is interesting, because Plato's router, NanoRoute, can also handle a flat design on a 32-bit workstation. Plato's customers can also use one router for both block- and chip-level routing, again lowering capital costs.

Although the market requires certain companies to generate new products from scratch with every generation, a significant number of companies modify products many times before producing a totally new design. Given the availability of silicon space that deep-submicron designs provide and the complexity of multimillion-gate designs, companies have embraced a new architectural method. It involves choosing a number of functional blocks that provide fundamental capabilities for products in given application areas, such as processors, controllers, DSP, and memories. These blocks are either produced in-house or licensed or purchased from third parties. The blocks are known-good and reliable and have been manufactured, at least on test wafers, in the target process. A collection of these blocks is called a platform. To obtain the desired product, a team of designers then adds logic blocks, removes some of the base blocks, and adds firmware. Figure 3, derived from a slide that Philips presented during a panel on deep-submicron challenges in October 2000, illustrates this platform-based design. The advantage of this development method is that it reduces the number of unknowns. It results in not only less design work, but also decreased verification time and simpler final-netlist generation.

The act of handing a design to a foundry for manufacturing is called "sign-off," because the customer certifies that the file represents the circuits he or she wants implemented, and the semiconductor company certifies that it will be able to manufacture the circuit it has received. There are three points in the design process when a design team can release its design to a semiconductor foundry for sign-off. The most common is at the completion of full placement and routing of the chip. A file in GDSII format contains the circuit topology, and the foundry uses it to produce the masks required for actual fabrication. The design can also be released at the gate-netlist level, allowing the semiconductor producer to complete final place and route. Sun Microsystems, for example, employs this method to offer its foundry partners the most flexible way to meet timing and power requirements.

A third sign-off time—at the RTL—is under discussion. The method has been the industry's goal for some time. It offers many benefits but, thus far, has been impractical. In this handoff method, the system company is responsible for the architectural design and the logic implementation of the product, and the semiconductor company performs the synthesis and place-and-route functions. The method does not require logic designers to know much about silicon physics. They just follow a set of design rules, provided by the foundry, aimed at avoiding a possible source of timing and power problems. Platform-based design methods are the likeliest to make RTL sign-off a reality. Companies such as NEC feel that an RTL sign-off method is close to becoming reality for platform-based designs. To close the design-productivity gap, a reliable method that allows designers to operate at the highest possible abstraction level is necessary.

Author Information

You can reach Technical Editor Gabe Moretti e-mail gabe@eda.org.