CPLD shrink combines speed, low power, and flexibility

With its recently introduced ispMACH 5000VG, Lattice Semiconductor took advantage of an advanced process lithography and the architecture enhancements it enabled to design a product family that combined the features of two previous ones. The company has chosen a similar strategy with its ispMACH 4000 (Picture), which supports 1.8V—a first for CPLDs—and 2.5V supply voltages, 1.8 to 3.3V outputs in two banks and, via configurable trip points, a variety of input voltages on an individual I/O-buffer basis. The ispMACH 4000 is architecturally based on the ispMACH 4A family that Lattice acquired when it bought AMD's programmable logic subsidiary, Vantis. Whereas ispMACH 4A parts had 33 to 36 inputs into each generic logic block, ispMACH 4000 parts, across the planned 32- to 512-macrocell range, all have 36 inputs. Lattice also added a five-product-term fast path that bypasses the macrocell and, therefore, also a synchronous register in favor of a simpler OR gate. The advantage is speed; in this mode, the parts' propagation delays are 2.5 nsec (32-macrocell device) to 3.5 nsec (512-macrocell device) with outputs driving 1.8V peak levels. The ispMACH 4000 parts can also optionally define a generic I/O pin as a global output enable, a mode that then doesn't consume internal logic resources to implement the function.

Lattice also focused on reducing power consumption, albeit not to the microamp levels of Xilinx's CoolRunner family, but without the CoolRunner's speed penalty. I_CC with input static ranges from 1 to 3 mA at 1.8V, depending on the device's macrocell count. Other features added to ispMACH 4000 and the ispMACH 5000VG family include the ability to allocate 80 product terms to a single macrocell, and I/O buffers with fast and slow slew-rate options, open drain, pullup, pulldown, bus-keeper, and no-connect output configurations and hot-socketing capability. The ispMACH 4256, now available, comes in 100- and 176-pin TQFP and 256-bump fine- pitch BGA packaging and will cost $6.50 (10,000) in the second half of 2002. The ispMACH 4512, also shipping now, comes in 176-pin TQFP and 256-bump fine-pitch BGA package options and will cost $15 (10,000) in the second half of 2002. Lattice plans to also release 32-, 64-, 128-, and 384-macrocell devices by June 2002. Also available now is ispLEVER design-tool support for the ispMACH 4256 and ispMACH 4512; contact the company for beta support on other devices in the ispMACH 4000 family.

Lattice Semiconductor, 1-503-268-8000, www.latticesemi.com.