Programmable logic appends to a blend

Lattice Semiconductor combines the wide-input-logic-block structure of the ispLSI 5000VE family and the high-density-conducive, dual-level-routing structure of the ispLSI 8000V architecture in the 768- and 1204-macrocell ispMACH 5000VG 3.3V CPLD product line. The logic-cell structure of ispMACH 5000VG delivers a key enhancement over its predecessor: The product-term-sharing array now enables you to allocate as many as 160 product terms to one macrocell versus the 35-per-macrocell limit of the ispLSI 5000VE.

Multitiered routing enables programmable-logic vendors to circumvent a global routing structure's cost-prohibitive exponential growth with increasing macrocell counts, but, in exchange, it complicates CPLDs' traditionally predictable timing. Partner UMC's (www.umc.com) advanced manufacturing process, though, delivers best-case 5-nsec and worst-case 6.5-nsec pin-to-pin asynchronous timing, along with 178-MHz clock rates. Speaking of pins, I/O-buffer flexibility is one of the two key enhancements that appear for the first time in a Lattice CPLD. The so-called sysIO feature allows for interface-protocol flexibility on a pin-by-pin basis (with common V_REF input and V_CCO output voltages) and block-by-block basis (independent of V_REF and V_CCO). Other low-voltage CMOS I/O-buffer capabilities include programmable drive current; fast and slow slew-rate options; open-drain, pullup, pulldown, bus-keeper, and no-connect output configurations; and hot-socketing capability with less-than-100-µA leakage current.

Dual integrated PLLs, which Lattice calls sysClocks, are the other key ispMACH 5000VG enhancement, delivering the ability to multiply and divide an incoming clock by a factor as large as 32, subject to a 5- to 180-MHz operating-range restriction, and to shift the clock forward and backward as much as 3.5 nsec in 500-psec increments. The PLLs tolerate cycle-to-cycle jitter of 100 psec, intraperiod jitter of as much as 200 psec, and lock within 30 µsec, and they offer both internal- and external-feedback options.

The ispMACH 51024VG is now available for sampling in 484- and 676-bump, 1-mm-pitch BGA packaging; projected price for the second half of 2001 is $50 (10,000). The ispLever design software, which comprehends the device's hierarchical routing, is also available. Lattice will offer the 4844-bump-BGA-package- and pinout-compatible ispMACH 5768VG for sampling by the end of the first quarter. Contact the company for beta-design-software availability. (See Picture.)

Lattice Semiconductor, 1-503-268-8000, www.latticesemi.com.