Ripples in the process pool

Look at any IC these days, and you'll see a combination of electrical performance, functions, size, and cost that vendors could not have attained just a few years ago. It's not that bright IC designers didn't populate the industry then. Many of the craft's best practitioners have been hard at work for decades. Rather, the stuff that IC manufacturers use to make their devices has been changing, enabling designs that not long ago were simply impractical and advancing those that were to new price and performance levels (see sidebar "How much Moore?").

Semiconductor processes have been evolving since John Bardeen, Walter Brattain, and William Shockley first observed the transistor effect more than a half-century ago. In the time since, OEM designers have done their jobs without a great deal of concern about the details of semiconductor processes. Unlike in years past, however, some of the largest applications for semiconductors benefit from the attributes of several widely disparate processes. Additionally, these processes enjoy sufficient capability overlap that the optimum choice of process or process combination is no longer obvious.

One result is that vendors are using their process choices as a means of differentiating their ICs. It's become part of the sell. As process designers continue to innovate, each recipe variation sends ripples through the process pool, which spread to IC-design teams, product-line management and marketers, and—eventually—you.

For a given process and over a range of die sizes, die costs are roughly proportional to area, so a biannual doubling of the active-device count is only half the story. By making smaller devices instead of bigger chips, innovations in semiconductor processing have caused the incremental cost for a given function to drop as precipitously as die complexity has increased. Smaller devices also allow faster signal and clocking speeds, so, measured in "processing power," semiconductors have enjoyed a per-unit-cost capability increase on a scale that society has never before seen in a commercial product.

Other technologies have for a time enjoyed steady exponential improvements until they hit some fundamental physical limit. For example, the aircraft industry improved air speed exponentially for some 40 years. In the 1960s, this decades-old upward trend abruptly flattened for commercial aircraft, and it has remained essentially flat ever since (Figure 1). Airfoil performance has largely constrained aircraft manufacturers from increasing air speeds beyond the speed of sound. Supersonic aircraft are a reality but not a particularly economic one; only one commercial aircraft design is in service today, and you could debate the extent of its commercial success.

In the electronics industry, a long string of process-chemistry and -equipment innovations has allowed us to thus far avoid similar collisions with physical constraints. One such limit, minimum feature size, has shrunk past the wavelength of light on its way from several microns to the submicron and deep-submicron regions. Meanwhile, the electrical characteristics of those semiconductors have changed, forcing some applications to stratify into distinct semiconductor process types. Consequently, the nonstop race for greater and greater levels of integration suggested by the oft-quoted Moore's Law shows signs of slowing as issues other than transistor count loom larger and nearer: Along with the ongoing buzz about so-called systems-on-chips, you can hear the low drone of qualifications and disclaimers.

A single "general-purpose" process no longer satisfies all the requirements of several of the largest applications. Chip-set designers' functional segmentation or product-partitioning exercises no longer simply determine which chips are digital, which are analog, and which are mixed-signal. More and more, they segment products according to which process best supports the needs of each functional block, and they allow the resulting segmentation map to guide decisions about integration levels.

The advantages of increasing levels of integration are legendary and not just limited to the raw cost per function. Smaller pc boards with fewer chips require less routing and result in fewer interactions. High levels of integration allow you to purchase packaged and tested functional subsystems, which reduces your design risk, time to market, and manufacturing costs. Product differentiation, always a challenge in fast-changing, highly competitive markets, moves from hard-wired to programmable features, which can reduce the your inventory costs and allow you to more opportunistically respond to market conditions. As for the base cost of silicon, the massive run rate of "vanilla" submicron CMOS, the small number of photomasks and process steps, and the enormous worldwide capacity makes this process the price leader square for square, against which the industry compares all others.

But not all functions benefit equally from the minimum feature size reductions that have made hyperintegration possible. Although deep-submicron processes have brought us economic processor cores operating at clock rates higher than 1 GHz, those processes support ever-decreasing supply voltages and signal swings. The process requirements of circuits that handle high-signal voltages diverge from the needs of core logic at about 1 µm, and low-voltage, precision-linear circuit requirements part company with logic processes at about 250 nm (Reference 1).

Some of the largest semiconductor applications beyond processor logic include mixed-signal application-specific products that often require far more from a semiconductor process than just speed and device density. For example, although some logic vendors are using 130-nm and smaller MOS processes, Alcatel recently announced the 350-nm I3T CMOS process for automotive and computer-peripheral applications.

A 350-nm process may sound like a giant step backward, but it is not. The process's minimum dimension is half the size of its predecessor, the company's I2T process. Unlike the most miniature logic processes that are limited to a couple of volts, I3T works with supplies as large as 80V for automotive ICs that must accommodate load-dump transients. I3T also supports the new 42V automotive standard and drive motors and actuators for computer peripherals and other small appliances.

Though less dense than the low-voltage deep-submicron processes, I3T offers an embedded ARM controller; USB and CAN (controller-area-network) controllers; flash, ROM, RAM, and OTP memory; and high-voltage DMOS switches with R_DS(ON) of 80 to 160 mΩ/mm².

Similarly, STMicroelectronics offers a range of larger-than-minimum processes to address power management and motor controls. One of these, the BCD6, is a 40V, 350-nm CMOS process that integrates microcontrollers, DSP cores, and nonvolatile memory with signal conditioning and power devices.

Historically, MOS emerged as the dominant process for logic ICs for a number of reasons. MOS fabrication requires few process steps and results in devices that take little area and dissipate little power, particularly at low frequencies. MOS devices have poorer transconductance than bipolar-junction transistors and a significantly higher 1/f noise corner frequency of about 10 kHz versus 10 Hz or less. Though these parameters are important for precision analog, they are not particularly critical for digital circuits, whereas MOS' scalability is a great advantage. You get to pack in more devices, and the smaller devices are faster—up to a point, that is.

Eventually, scaling MOS devices becomes difficult. As gate lengths shrink, devices begin to show evidence of subthreshold leakage, a condition in which the gate cannot hold off the channel current. Also at these extremes, the drain voltage's effect on the depletion region at the drain/channel interface can modulate the device's threshold—the so-called short-channel effect. With short-channel devices, the drain capacitance doesn't scale with the other device parameters unless the fabrication process makes shallower implants. (Note that in some of the literature, doped active regions are referred to as "diffusions," irrespective of whether the fabrication method is diffusion or ion implantation.)

You can calculate the minimum channel length, L_MIN, for a given MOS process. This dimension has a cube-root relationship to the gate-oxide thickness, the source and drain depletion-layer widths, and the depth of the pn junctions associated with the source/drain implants into either the substrate silicon or the well. Further shrinking the process is not just a photolithographic problem. You have to make shallower implants, thinner oxides, and smaller depletion-layer widths, which require tighter process control and lower operating voltages (Reference 2).

You can see this relationship at work when you compare process generations within a single vendor. For example, one CMOS foundry, Silterra, uses 100Å gate oxide for the company's 500-nm process running at 5V. By comparison, its 130-nm CMOS13 process uses a 20Å gate oxide and makes devices that operate on 1.2V. To make circuits that can connect to common I/O structures, CMOS13 also has a thick gate oxide for larger-than-minimum devices that can operate on 3.3V rails.

Small device dimensions and operating voltages have been a boon for logic designers. Smaller dimensions suggest smaller stray capacitances, and smaller signal swings suggest lower power dissipation. Both of these properties are good for making high-speed processors. But, though further miniaturization of devices enables faster devices and extends the utility of CMOS technologies, it doesn't change the dissipative mechanisms. CMOS capacitive losses remain proportional to switching speed, substrate capacitances don't scale directly in proportion to device geometry, and leakage currents increase with shrinking geometries. Although, at moderate speeds, CMOS is known as the "low-power" process, the high-speed versions of the technology are not necessarily so.

A number of methods exist for reducing the substrate losses and mitigating the lower physical limits to device size. SOI (silicon-on-insulator) technologies address these problems by replacing the conductive bulk substrate—or at least the portion closest to the active regions—with a nonconductive one. Many of the largest semiconductor vendors have disregarded SOI technologies on the basis that they could continue meeting the market's demand for high-speed circuits using low-cost standard CMOS. But even Intel, which has pursued CMOS-on-silicon process development to the tens-of-nano-meter scale, recently announced that it is looking to SOI for future process development (Reference 3). With deep-submicron CMOS challenged on both operating-voltage and RF-power-dissipation fronts, SOI processes are also attractive in applications as varied as automotive, telecomm, and communications physical layer.

Fabricators can implement SOI processes in several ways. The bonded-wafer SOI process begins by growing oxide layers on two silicon wafers (Figure 2). The oxide surfaces have an affinity to one another, so when they come together face to face through a thermal cycle, the oxides grow together and form a solid bond. A polishing step thins one silicon surface to a specified thickness for use in forming the active circuit regions (Reference 4). Bonded SOI wafers, such as those that Analog Devices' XFCB and National Semiconductor's VIP10 CB processes use, are popular among linear designers because they produce fewer surface defects than other SOI methods. As a result, bonded wafers have historically exhibited better parametric behavior, including lower 1/f noise, than similar devices formed on other SOI processes. Along with lower parasitic capacitances, complementary bipolar-on-SOI processes also offer low parasitic resistances for a high ratio of bandwidth to power dissipation. These attributes are attractive for low-distortion front-end applications ranging from xDSL and wireless LAN to DVD players.

In SIMOX (separation by implantation of oxygen or silicon implanted with oxygen), an ion implanter drives ionized oxygen into the silicon lattice in much the same way implanters drive dopants into the lattice to form active semiconductor regions (Figure 3). However, the SIMOX implanter's acceleration potential, which controls the implantation depth, is large enough to drive the oxigen ions well below the surface, leaving an unoxidized silicon region available to form circuits over the buried oxide. To prevent charge from building up on the wafer, an electron source covers the wafer with a blanket of electrons. The current measured from the back of the wafer is a measure of the ion-implant rate, a quantity the process can use as a measure of the ion dose.

A third process, LEO (lateral-epitaxial-overgrowth)-SOI, seeds a single-crystal silicon epitaxial layer and grows it over an oxide (Figure 4). Historically, the challenges to LEO and SIMOX include maintaining the single-crystal structure during lateral epitaxy and alleviating lattice damage after oxygen-ion implantation, but the technologies have been evolving with newer process variants alleviating these problems.

Building SOI on thick oxide reduces parasitic capacitances, but, at radio frequencies, it still suffers from body effects that reduce gain and linearity in analog circuits (Reference 5). Peregrine's SOI process attempts to solve this problem by eliminating the dielectric sandwich formed of active silicon, the buried SIMOX oxide, and the substrate silicon.

Peregrine builds on the SOS (silicon-on-sapphire)-SOI process Rockwell Semiconductor (now Conexant) pioneered in the 1960s. Sapphire may sound like an outrageously exotic substrate material, perhaps more suitable to a back-of-the-jewelry-store fabricator than to a commercial process. But recall that sapphire is aluminum-oxide, which is chemically identical to common alumina ceramic. However, sapphire is a single crystal, whereas alumina is a polycrystalline structure with a few to several percentage points of amorphous aluminum oxide binding the bits together.

Early attempts at SOS processes resulted in poor lattice quality, producing low-yielding wafers. The sapphire and silicon lattices match poorly, so epitaxial silicon deposition on sapphire leaves dislocation defects in the silicon. Peregrine's UTSI process implants silicon into the epi layer with sufficient energy that the lower two-thirds of the epitaxial film amorphizes. An annealing step promotes silicon at the surface with a 1-0-0 orientation to grow into the amorphous region all the way to the sapphire substrate. An oxidation step followed by an oxide etch leaves an ultrathin single crystal silicon film on the sapphire substrate. CMOS devices formed on the thin film lack the usual parasitic substrate capacitances found in bulk silicon CMOS processes. Additionally, by fully depleting the silicon film, SOS-SOI devices enjoy improved linearity and speed.

Peregrine's SOS-SOI process claims an f_MAX at 250 nm of about 85 GHz compared with 40 to 60 GHz for popular foundry bulk-CMOS processes at 130 nm. The larger geometry SOS devices also operate at twice the voltage as the smaller bulk-CMOS devices with benefits to the circuit's dynamic range.

Passive devices represent a significant challenge to mixed-signal-chip manufacturers and their customers. Many OEMs are less concerned with seeing a three-chip set reduced to one integrated device than they are seeing the 300 accompanying passive components reduced to 30. But most IC processes don't make space-efficient passive components, and those that they do make are often parametrically far inferior to discrete passives. With analog front ends operating in the tens of gigahertz, IC designers don't want to take a signal off-chip unless they have to. The chip-to-board parasitics create performance and power-budget problems.

SOI technologies help fabricators make better RF passive devices. Processes that support thick top-layer metal can form inductors with Q factors four to five times that seen in bulk-silicon processes with greater self-resonance frequencies. When IC designers use these devices in conjunction with high-Q metal-insulator-metal capacitors, they can lay out high-performance matching circuits and tuned elements on-chip.

Though SOI-IC manufacturers can take advantage of their processes' high Q passives, those devices still consume significantly more area than do active devices. Intarsia, a manufacturer of RF MCMs (multichip modules), has developed a thin-film-on-glass process to take advantage of the fact that passive—not active—devices dominate some RF functions for broadband wireless, cellular base stations, wireless LANs, and GPS (global-positioning-system) devices. MCM packaging allows Intarsia to couple high-Q, low-loss, RF passive networks with active circuits, which can use standard on-chip aluminum interconnects (Figure 5). As an example, a complete low-noise amplifier may have 11 passive devices and one active component. Using their thin-film-on-glass MCM process, Intarsia has produced several low-noise amps with fractional-decibel noise figures spanning the 0.8- to 6-GHz range, including 802.11a, 802.11b, and Bluetooth.

Eventually, the speed-for-dynamic-range swap runs out of dynamic range to trade, and power dissipation rises to feed the parasitics growing with every exchange. At this point in silicon-process evolution, process engineers may squeeze still more performance from standard silicon processes with further miniaturization, but the decreasing gains are harder to come by.

Fortunately, alloys are synergistic; that is, they can have attributes superior to those of their constituents. A case in point, using graded germanium doping in a transistor's base region can make the base transit time for a given geometry significantly shorter than using either silicon or germanium alone. The shorter base transit time increases the unity current-gain bandwidth, f_T, and the proportional unity power-gain bandwidth, f_MAX. SiGe (silicon-germanium) processes, which IBM developed, have enjoyed a good amount of refinement in the last few years. In the meantime, they have emerged from the category of "boutique" processes to the mainstream with a long list of vendors offering the technology. These manufacturers include AMCC, Atmel, Conexant, Motorola, SiGe Semiconductor, Sony, and STMicroelectronics and foundries, such as IBM and TSMC.

Compound semiconductor processes, such as GaAs (gallium arsenide) and InP (indium phosphide), have greater carrier mobilities and are, therefore, still faster than silicon or SiGe. The compound semiconductors also offer their greater speeds with larger-voltage handling capability. But for, say, OC-192- and 10-Gbit Ethernet-class data rates, current-generation SiGe processes are fast enough. SiGe processes have the added advantage of using the same starting material and running on the same fabrication equipment as do the all-silicon processes. This compatibility allows SiGe to benefit from the same high levels of integration as similarly scaled standard silicon processes while improving the speed for a given operating current (Reference 6).

Some might tell you to grab your life jacket. Others may scrawl dark messages on technology maps: "Beyond here, there be dragons!" But take heart that a well-charted ocean lies beyond the comfortable silicon waters. Compound semiconductors have been floating around in the highest frequency applications for many years, but the semiconductor industry has traditionally relegated them to the commercial backwaters. These semiconductors are formed of Group three elements, such as gallium and indium, and Group five elements, such as phosphorous and arsenic. However, in recent years the winds of change and a rising tide in photonic applications have lifted compound semiconductors and billowed their economies of sail... errr... scale.

At the electrophotonic interface communications signals demand the most of high-speed processes and design methods. This spectral region reminds us that, though they may represent data streams, all signals are analog. Despite the current market doldrums, communications traffic continues to rise, and many believe that the metro network will require 40-Gbps OC-768 data rates even before the core network does.

Little doubt exists that parallel structures from the framer on the back will continue in silicon-CMOS processes, which follow well characterized performance curves and cost structures in the region of 2.5G words/sec. But the physical layer's 40-Gbps serial-data stream requires f_Ts of 100 to 200 GHz, depending on the data-coding method the application employs. Bipolar devices enjoy an advantage at these speeds because epitaxial structure—not lithographic tolerances—determines device parameters. In contrast MOS device parameters are more sensitive to lithographic tolerances (Reference 7). Additionally, IC designers can compensate bipolar transistors more easily than MOS devices for behavioral variations over their operating range, although at least one new process, Impinj's self-adaptive silicon, tries to remedy MOS' weakness in that regard (see sidebar "Impinging on bipolar").

Current generation SiGe devices exhibit peak f_Ts of about 125 GHz at current densities near 7 mA/µm² but with low breakdown voltages. Current-generation InP processes make heterojunction-bipolar transistors with gain-bandwidth products of 200 GHz at current densities of little more than 1 mA/µm² (Figure 6). Even next-generation SiGe, which some expect to turn in peak f_Ts in the neighborhood of 200 GHz, will do so at about an order of magnitude greater current density—about 10 mA/µm²—and still poorer signal ranges.

Vendors such as Inphi and Vitesse are turning to InP technologies to gain greater speed at lower power and with greater operating voltage capability. Mixed-process InP/CMOS OC-768-transceiver modules combine the speed and power-dissipation advantage of InP with the integration advantage of CMOS and keep their power consumption on par with OC-192 transceivers in SiGe (Figure 7, Reference 8).

The electro-optical properties of InP allow vendors to integrate PIN photo-diode detectors and their associated transimpedance amplifiers on one chip, which reduces parasitic loading and package count. Vendors are also working on integrating the PIN, transimpedance amplifier, and postamplifier in one device. Similar near-term integrations of, say, a vertical-cavity surface-emitting laser, a modulator, and a driver are less likely, particularly if designers need to maintain high extinction ratios from the modulator. Vendors are looking to integrate the 4-to-1 multiplexer, clock-multiplier unit, 1-to-4 multiplexer, and clock- and data-recovery circuit, as well as the 16-to-4 CMOS multiplexer with the 4-to-16 CMOS demultiplexer.

As InP processes mature further, several vendors are offering foundry services. The compound semiconductor processes are not a panacea. The starting materials are more expensive per unit area than silicon. Three/five processes tend to run 4-in. or smaller wafers in an age in which 6-in. silicon lines have largely given way to 8-in., with 12-in. lines coming onboard. Three/five processes also use different equipment and step flows, making those processes incompatible with standard silicon fabs. By contrast, SiGe uses the same starting material and equipment and many of the same chemistries and steps as silicon. Three/five compound semiconductors also don't form a native oxide and so cannot take advantage of the self-masking and -passivating steps that silicon processes do. But the capabilities of the three/five processes are attractive for circuits that must operate at the highest frequencies, handle large signal amplitudes, or constrain noise and power consumption.

In the end, you need to determine where your circuit needs such performance and take advantage of appropriate levels of integration as such opportunities present themselves. By maintaining an agnostic outlook on IC processes, you can evaluate what each vendor offers and use your knowledge of the processes' capabilities to guide your questions as you check the veracity of a manufacturer's claims.

Keep in mind that the decision points are not static; they're carved in sand, not stone. Which process best serves different parts of your design changes, as those processes evolve. According to Analog Devices' David Robertson, this sort of partitioning and integration strategy, in which you implement functions on the most appropriate process technology, is displacing the old strategy of separating devices according to their "analog" or "digital" content, particularly among multiprocess vendors of functional chip sets. You can see the same trend in many disparate applications that share the common attribute that different blocks demand different speed, signal-swing, and load-current capabilities.

That said, small vendors often have to push with what they have and go with what they know. Companies that choose CMOS benefit from a global capacity far and away greater and at prices meaningfully lower than those of any other process. The most readily available CMOS processes also correlate well to their simulation models, reducing the fab cycles before a product release. It is no surprise that many of the fabless-semiconductor companies specialize in CMOS.

You may have wondered whether "fabless" was simply synonymous with "productless" during these vendors' early histories. However, several have turned in excellent designs with innovative features in areas such as physical-layer chips for Gigabit Ethernet, OC-48, 802.11b, and 802.11a, in which many until recently doubted whether CMOS would perform adequately. TSMC and other pure-play foundries have started to offer other processes, most notably SiGe. Multiprocess-IC vendors, such as STMicroelectronics and Vitesse, are also offering foundry services to fabless companies. How quickly the fabless companies adopt processes other than CMOS will depend on the competitive demands of their markets, the cost and quality of the design-tool suite, and the companies' abilities to adapt their design methods to the different processes.

Author Information

You can reach Technical Editor Joshua Israelsohn at 1-617-558-4427, fax 1-617-558-4470, e-mail jisraelsohn@cahners.com.