ADC preamplifier works the gain/dynamic-range trade-off to achieve 14-bit linearity

System designers in many fields continually strive to increase the speed and precision in their analog-signal-processing chain by upgrading the ADC (Figure 1). In the ADC realm, the units of speed and precision are samples per second and effective number of bits, respectively. Unfortunately, a designer cannot increase the speed and precision of an analog-signal-processing chain by merely using a better data converter, because the quality of the input signal can limit converter performance. For this reason, the designer must give equal attention to the design of the ADC preamplifier to maximize the performance of the system.

The design of an ADC preamplifier revolves around noise and distortion. Noise and distortion represent undesirable signal content that can degrade the performance of the entire signal-processing chain. If the gain block before the ADC contributes noise or distortion at or near the power levels of the ADC's minimum detectable signal, the undesirable signal content can mask the presence or absence of real signal information and effectively reduce the precision of the signal.

To prevent amplifier performance from limiting system performance, system designers set amplifier-distortion targets equal to or, preferably, below the threshold for the desired precision of the data converter. As an example, a 14-bit system requires distortion to be at least –86 dBFS (decibels relative to full-scale) range of the data converter. The relationship between the effective number of bits and the SINAD (signal-to-noise-and-distortion) metric is as follows:

The design goals for a low-noise, low-distortion, high-gain circuit that provides 14-bit linearity for signals with frequencies surpassing 30 MHz (Figure 2) are as follows:

• to minimize distortion, particularly distortion components that are difficult to filter;
• to minimize noise, such that it doesn't influence the ADC dynamic range;
• to provide gain to relax the distortion requirements on previous stages in the signal-processing chain; and
• to perform single-ended-to-differential conversion to maximize ADC performance and to suppress even-order distortion products.

These goals imply several fundamental trade-offs. The most critical is the need for both high gain and low distortion. Distortion in a closed-loop system is inversely proportional to the amount of excess loop gain at any given frequency. Thus, for a given amplifier, distortion performance degrades as the gain of the amplifier increases.

The circuit in Figure 2 uses a combination of techniques to address this trade-off. The circuit uses decompensated amplifiers with external-compensation techniques, and the transformer improves the circuit's noise figure while converting a single-ended input signal to a differential signal. External compensation shapes the noise gain of the amplifiers in a way that maintains stability and increases the excess loop gain at the frequencies of interest. The circuit simultaneously achieves high voltage gain, large SFDR (spurious-free dynamic range), and low noise (Table 1).

The circuit begins with an RF transformer with a 1-to-2 turns ratio at the input. The transformer provides a voltage gain of 2V/V, accomplishes the task of single-ended-to-differential conversion, matches the two gain-setting resistors to the expected 50Ω source impedance, and uses the source impedance to decrease the low-frequency noise gain of the circuit. These attributes impact the total circuit's overall gain, noise figure, and distortion characteristics. The differential outputs of the transformer provide two out-of-phase inputs to two identical sub-circuits. Each transformer output leads to an OPA687 that the circuit configures for an inverting gain of –10V/V. Because internal compensation keeps the OPA687 stable when the noise gain is 12V/V or higher, an external compensation scheme using capacitors in the feedback path and on the inverting input is necessary. The outputs of the two OPA687 devices provide a very linear differential output signal. Click here for a bill of materials for this circuit.

Many variants of this circuit are possible, depending on the requirements of the signal-acquisition system. For example, an alternative circuit achieves a different mix of characteristics for gain, noise, and distortion performance (Reference 1).

The decompensated amplifiers in the circuit are the keys to obtaining the superior distortion performance. However, the design requires an external compensation scheme to maintain stability in the decompensated amplifiers.

Fundamentally, distortion in an amplifier is the combination of intrinsic amplifier nonlinearity and the curative effect of negative feedback upon this nonlinearity. The ability to correct for nonlinearity is directly related to the amount of excess loop gain in the system. Because the open-loop gain of an amplifier rolls off as frequency increases, the excess loop gain decreases proportionately for a frequency-independent feedback factor. Therefore, distortion performance in an amplifier typically degrades as frequencies increase.

The increased gain-bandwidth product of decompensated amplifiers provides circuit designers with the ability to manage the excess loop gain more effectively than is possible with an amplifier that is unity-gain stable. With an external compensation scheme, decompensated amplifiers can operate at a gain less than the minimum stable gain, as long as the external compensation capacitors shape the noise gain such that the noise gain exceeds the minimum stable gain at the noise gain's intersection with the open-loop gain characteristic (Figure 3).

The circuit configures each amplifier for an inverting gain of –10V/V from the perspective of the signal exiting the transformer. However, the noise gain of each amplifier is 6V/V, which is less than the minimum stable gain. The relationship between the noise gain, and the external-component impedances is:

where NG is noise gain. At low frequencies, Z_F and Z_G are purely resistive. Z_F is equal to the 1-kΩ feedback resistor, and Z_G is equal to the sum of the 100Ω gain-setting resistor plus half of the source resistance reflected through the 1-to-2 transformer. The circuit reflects the source resistance through the transformer by an ohm ratio of 1 to 4. Therefore, the 50Ω source impedance reflects through the transformer as 200Ω, half of which appears on each output of the transformer. This effect yields an effective Z_G of 200Ω at low frequencies. Therefore, each amplifier has a low-frequency noise gain of 6V/V. At low frequencies, the circuit has an additional 6 dB of excess loop gain compared with the same amplifier operating at its minimum stable gain in noninverting mode. This improvement translates directly into enhanced distortion performance.

The compensation capacitors, C_G and C_F, shape the noise gain at high frequencies, maintaining amplifier stability. As mentioned, the noise gain must equal or exceed the minimum stable gain when the noise-gain curve intersects the open-loop gain curve. Additionally, the rate of closure between the two curves must be 20 dB per decade to achieve a stable system.

Capacitor C_G introduces a zero in the noise gain to push the noise gain above the minimum stable gain as the frequency increases, and capacitor C_F introduces a pole in the noise gain to reduce the rate of closure to 20 dB per decade. The values of C_F and C_G provide a high-frequency noise gain of 18V/V, which substantially exceeds the minimum stable gain. They also provide a pole to achieve the maximally flat bandwidth. The sidebar "Choose compensation capacitors for maximally flat bandwidth" outlines the design process for choosing C_F and C_G. Reference 2 gives full derivations of these equations.

The key performance metric for this circuit is the distortion behavior over the frequency band of interest. The intermodulation distortion is of particular interest because it is typically the worst-case distortion product that is not susceptible to filtering. Figure 4 and Figure 5 present distortion curves (HD₂, HD₃, and IMD₃) for a 2V p-p differential output signal and the third-order output intercept point (OIP₃). Test conditions for distortion testing included an 800Ω differential load and a 2V p-p output-signal envelope. The measurement system limited accuracy to approximately 95 to 100 dB of dynamic range under these conditions.

Third-order intermodulation products for a 2V p-p signal envelope exceed the requirement for 14-bit linearity up through approximately 40 MHz. Harmonic-distortion measurements are included for completeness, although the required antialiasing filter at the interface between the amplifier network and the ADC drastically attenuates most second- and third-order harmonic-distortion components. Because the second and third harmonics occur at frequencies that are double and triple the fundamental frequency, you can relatively easily filter out these harmonic products. Typically, second- or third-order filters are sharp enough to attenuate the second- and third-order harmonic products to a level well below the third-order intermodulation-distortion products. Therefore, IMD₃ typically dictates the SFDR at the input to the ADC.

The two-tone third-order intermodulation-distortion measurements determine the third-order output-intercept point (OIP₃) for the circuit (see sidebar "A primer on intermodulation distortion and intercept points"). The measurements include values that exceed 30 dBm for frequencies as high as 50 MHz, including an OIP₃ of 40 dBm at 30 MHz (Figure 5).

Designing for low noise is also a consideration for this circuit. The decompensated amplifiers and a 1-to-2 transformer on the input reduce the circuit's noise figure to 5.2 dB. Given that the circuit constrains the gain-setting resistors to match the 50Ω source through the transformer (Reference 3), the following equation defines the circuit's noise figure:

where n is the turns ratio, e_N is the amplifier input voltage noise, i_N is the inverting input current noise, K is Boltzmann's constant, T is temperature in degrees Kelvin, and α is R_F/R_G.

Due to the noise-shaping scheme that increases the excess loop gain at low frequencies and stability at high frequencies, the output noise increases with frequency. However, this effect typically has little bearing on the circuit's performance in a system because the antialiasing filter attenuates the high-frequency noise before the data converter. As the noise-figure equation indicates, designers have some control over the noise by altering the gain of the system.

The combination of the high gain-bandwidth product of the decompensated amplifiers and the desire for 14-bit linearity at frequencies exceeding 30 MHz force you to pay close attention to the design of the pc board as well as the circuit. Design techniques include careful minimization of high-frequency current paths, proper power-supply bypassing, and advantageous use of the SOT-23-pin configuration.

The SOT-23-pin configuration allows for optimal control of the ground plane at points of interest and minimizes the return current paths of the output signal. Using a two-sided board, a pc-board designer can place two SOT-23 devices directly opposite each other (Figure 6). This placement provides two key advantages. First, the positive power-supply pin of one device is adjacent to the negative power-supply pin of the second device on the opposite side of the board. Therefore, side-by-side placement of power-supply bypass capacitors becomes simple, providing a common ground connection. Placing these capacitors right next to the device is possible with only a single via separating one of the capacitors from the pin. This placement provides an extremely short output-current return path, which minimizes the opportunity for extraneous signals to couple into the output and affect the dynamic range. This phenomenon typically affects even-order harmonic-distortion products.

Second, the device arrangement allows for a second common-ground point at the noninverting nodes of the two amplifiers (Figure 7). For this circuit, the noninverting nodes are held at ground, but any difference between the grounds affects the symmetry of the circuit performance. Coupling of signals into this node could also potentially influence the dynamic range. If any extraneous signals in the ground path are present at both of the noninverting inputs as a common-mode signal, this circuit rejects those signals. This arrangement connects the noninverting nodes, with a single via directly underneath the part, with a separation distance on the order of the dimensions of the SOT-23 package. In this configuration, any noise in the ground plane has little opportunity to appear as anything but a common-mode signal.