The PLD (programmable-logic-device) code in Listing 1 creates arbitrary-resolution, pulse-width-modulated (PWM) generators. PWM generators are useful as low-bandwidth D/A converters in hardware of microprocessor-based systems. When you pass it through a simple RC lowpass filter, a PWM waveform becomes a voltage that's approximately equal to the PWM duty cycle times the supply voltage. In practical systems, the driving hardware is imperfect, so the minimum value is never zero, and the maximum value never equals the positive-voltage rail.

The software module in Listing 1 automatically generates the required hardware from two compile-time parameters: PWM_WIDTH and AVALUE. PWM_WIDTH sets the number of possible steps in the PWM comparison. For example, 6 bits yields 2⁶, or 64, steps. AVALUE sets the value at which the PWM initializes upon power-up or reset (set to one-half scale in the example in Listing 1).

The module has two major sections: a holding register, which stores the PWM value, and a counter, which generates the PWM waveform. You can update the holding register independently of the PWM counter. The holding register's value automatically strobes into the PWM counter when the counter overflows. The module takes the CLOCK, ACLR, ENABLE, WRITE, and DATA[PWM_WIDTH-1..0] inputs. CLOCK is the master system clock; all signals other than ACLR must be synchronous with the clock's rising edge. ACLR initializes the hardware to the power-up state and loads AVALUE into the holding register. When ENABLE=0, the PWM output becomes 0 (off); when ENABLE=1, the PWM generator produces the PWM waveform at the Q output. Asserting WRITE for one clock cycle strobes the data presented on DATA[PWM_WIDTH-1..0] into the holding register. The PLD code uses Altera's (www.altera.com) AHDL high-level design language; you can directly compile the code into any of Altera's PLDs. Using an EP1K10TC100-3 PLD, a design with parameters set to the default values in Listing 1 operates as fast as 139 MHz. Although we wrote the code for Altera's devices, you can readily translate the design structure and flow into VHDL or Verilog.

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