Tensilica's Xtensa V architecture builds on its predecessor's focus for integrating multiple unique and task-optimized processors in an SOC (system-on-chip) design. Architectural enhancements include supporting multicycle and nondeterministic devices through the XLMI (Xtensa local-memory interface). This approach allows the system to stall single-function task engines so that they can more easily coordinate and share memory and processor resources with tightly coupled devices that are multicycle or that exhibit nondeterministic behavior. Another interface enhancement enables Xtensa to simultaneously execute instructions and handle read and writes to the processor's local data memory from external agents, such as DMA engines. These enhancements facilitate better processor-to-processor and RTL-to-processor communication.

A new write-back cache option can reduce system-bus traffic for systems that use shared-memory architectures. The instruction-set architecture includes a new processor-ID register that can uniquely identify each processor in an SOC design without any external logic or synchronization mechanisms. This approach is beneficial for software development and integration in which the same processor configuration exists as multiple instances, such as for networking applications that are inherently parallel applications. The TIE (Tensilica Instruction Extension) language includes new constructs to support user-defined, conditional load-and-store instructions that can improve system performance by reducing the number of branch instructions a program needs to execute.

The C/C++-compiler enhancements include better optimization of function inlining, including cross-file inlining and more aggressive removal of unused code. Enhancements to the register scheduling and alias-analysis engine improve the C-code variable handling and performance. Applications using the Vectra DSP engine will benefit from a more comprehensive vectorization and "SIMD-ization" engine. These enhancements deliver a 5 to 10% reduction in code size and as much as a 50% improvement in non-hand-optimized C-code execution performance over the previous compiler.

The Xtensa V features will become available in the third quarter of 2002. Price is a licensing fee per processor instance plus royalties based upon the volume of processors manufactured. The licensing fee for a single processor configuration, including a complete, configured Gnu-based software-development tool set, starts at $350,000. The standard license deliverables include source Verilog or VHDL RTL plus supporting EDA-tool scripts, a test suite, placement guidelines, and the customized software tool set. The Xtensa C/C++ compiler, Xtensa instruction-set simulator, and Xtensa TIE compiler are priced separately.

Tensilica, 1-408-986-8000, www.tensilica.com.