The PLD (programmable-logic-device) code in Listing 1 implements a pc-board-level revision-detection system that detects whether PLD pins are shorted together on a pc board. It is often advantageous to field a single PLD programming file that works for several generations of physical hardware. The PLD needs to understand what the board revision is, so that it can enable or disable functions, pins, or both to external circuitry. If a designer has not placed physical straps to indicate a pc-board-revision level from the start, it may be difficult to add them later. In PLD families that have no integral pin-pullup or -pulldown resistors, redefining previously unused pins as inputs means that these pins float, either causing erratic operation or indicating an improper pc-board-revision level.

The software module generates a short, simple pattern, such as a square wave, onto a driver pin, REVO_OUT. The input-detection pins, REVI_IN[x], look for this pattern. If they detect the full pattern on a pin, the module indicates that the pins are connected by setting the respective Q[x] high. If they do not detect the full pattern, the module sets the Q[x] line low. The pattern generator avoids leaving the revision-detection inputs floating by alternately driving and tri-stating the REVO_OUT and REVI_IN[x] lines (Table 1). If you drive the circuit at more than a few megahertz, the parasitic pin capacitance of a few picofarads is sufficient to ensure that the REV_I[x] pins stay low, even while they are tristated. When the detection cycle is finished, the COMPLETE line goes high.

The module generates the required hardware from two compile-time parameters: LPM_WIDTH and CHANNELS. LPM_WIDTH sets the number of times the detection cycle runs (for example, 5 bits yields 2⁵, or 32 cycles), and CHANNELS sets the number of strap inputs. Note that this function does not include tristate buffers; you must instantiate them at the design top level. The REVO_EN and REVI_EN pins enable the REVO_OUT and the REVI_IN[x] tri-state buffers, respectively. The PLD code is written in Altera's (www.altera.com) high-level design language (AHDL); you can directly compile it into any of Altera's PLDs. An implementation of the design with the parameters set to the default values takes 16 logic cells in an Altera EP1K50BC256-3—less than 1% of the device—and runs at rates as high as 185 MHz. Although the code is written for Altera's devices, the design structure and flow are readily translatable into VHDL or Verilog.

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