Power sequencing poses a unique problem in power management. Because improper sequencing may cause damage to many types of processors, power-up sequencing of these devices is critical. Devices that may require power-up sequencing control include FPGAs, ASICs, and DSP chips. These devices can require tracking I/O and core voltages. Requirements for power-up sequencing may change according to device type and manufacturer, so it's important that you review sequencing requirements for each device. This design use Xilinx's (www.xilinx.com) power-up requirements for the Spartan-II and Spartan-IIE families. The I/O voltage must reach full supply voltage in 2 to 50 msec. Also, the slew rate of the supply voltage must not exceed 900 mV/msec but must exceed 50 mV/msec. The circuit in Figure 1 addresses these issues, allowing for consistent and reliable power-up sequencing.

The power-up sequencing circuit uses an RC (R₃ and C₃) timing network to control the slew rate of the output during turn-on. IC₂ compares the output of the low-dropout regulator with the voltage at the RC network. It then adjusts the output of the regulator, via the feedback voltage, to match the RC charge voltage. When the voltage between R₃ and C₃ reaches the low-dropout regulator's regulation voltage, the output of IC₂ pulls low, reverse-biasing D₁, thereby removing the power-up sequencing circuit from the control loop. R₄ and C₄ provide compensation to maintain a smooth voltage during the turn-on cycle. R₁ and R₂ provide the output regulation voltage. You can calculate R₁ and R₂ from the following expression: R₁=R₂(V_OUT/1.240–1). Figure 2 shows slewing characteristics of the output with various values of C₃.

Figure 3 is an I/O and core-voltage-sequencing circuit. Instead of using an RC charge voltage to control the turn-on, IC₃ of the core regulator compares the output of the I/O during turn-on and matches the core voltage until it reaches the regulation voltage. Figure 4 shows the I/O and core voltages during the power-on cycle. Equally important is the power-down cycle. The I/O voltage must never reach 0.6V below the core voltage. This condition can forward-bias the substrate diode, damaging the processor. D₂, a Schottky diode with a forward voltage drop of 0.4V, keeps the I/O voltage from dropping 0.6V below the core voltage during the power-down cycle (Figure 5).

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