Selecting passive components for PLLs

PLLs (phase-lock loops) in SERDES (serializer/deserializer) components control the frequency output of a VCO (voltage-controlled oscillator) to match a clock reference. Because both the reference and the VCO are independently noisy, the choice of components in the PLL involves trade-offs. In a PLL, control circuitry acts upon the phase difference derived from a reference clock, R, and the divided-down version of the output clock, Y (Figure 1). The control circuit commands the VCO, which converts a voltage quantity into a frequency. The factor n may be 1, depending on the ratio between the reference and the output frequencies.

When depicting the general circuitry of a PLL as a Laplace-transform mathematical model, quantities such as R(s) and Y(s) are Laplace transforms of the frequencies of the signals r(t) and y(t), not of the signals themselves. Thus, you can assume the work of the phase detector to be the subtraction of the phases of the reference and divided output clocks. Representations of PLLs, such as this one, discuss dynamics in terms of the content of the frequencies themselves. You can think of any component of R(s) or Y(s), where s is not 0, as a modulation of the steady-state frequencies R(0) or Y(0).

A pole at 0 Hz with a gain and an added term, N(s), which signifies the inherent noise inside the VCO, together represent the VCO dynamics. The N(s) term leads to a trade-off that ultimately results in an optimal range for the bandwidth of the PLL. Too high a bandwidth allows noise on r(t) to pass to y(t). Too low a bandwidth impedes the PLL's ability to oppose n(t)'s passage to y(t).

A sample H(s) compensation-scheme circuit takes a differential phase-detector output voltage and generates a voltage-control signal for a VCO (Figure 2). Such a circuit can, for example, interface the SERDES component with a VCXO (voltage-controlled crystal oscillator) in a jitter-cleanup application. The SERDES takes as an input the output of a VCXO, which uses c(t) as its control voltage. The SERDES develops pd(t) by comparing c(t) with a reference, r(t), via its internal phase detector. Equation 1 lists the circuit's Laplace transform.

EQUATION 1

This compensation scheme contains one pole at 0 and one zero at –1/CR₂. By using this H(s) and the chosen VCO model of k/s+N(s), you can derive the closed-loop dynamics of the system. More elaborate control schemes that give rise to different sets of compensation poles and zeros from those of H(s) are also available. Analysis and understanding of this simple scheme, though, are sufficient to spawn a method for optimizing components to deliver the best performance.

Starting with Figure 1 and using H(s) and a model for the VCO enables the derivation of Equation 2 for the output Y(s):

EQUATION 2

More specifically, equations 3 and 4 show the closed-loop transfer functions from the reference frequency, R(s), and the noise source, N(s), to the output frequency, Y(s).

       EQUATION 3

   EQUATION 4

Although these two transfer functions contain the same poles, the difference in their zeros produces significantly dynamic contrasts. The transfer function Y/R contains one zero and two poles. Because none of the poles or zeros are at 0, this transfer function has a finite, nonzero dc gain. In fact, the gain is n, which makes sense, because in a steady-state condition, the frequency of y(t) is n times the frequency of r(t). With two poles and only one zero, the transfer function rolls off at high frequencies. Thus, although the PLL can successfully track low-frequency perturbations of the steady-state frequency of r(t), high-frequency deviations of r(t) do not pass to y(t). This filtering of higher frequency r(t) content is desirable, because a typical function of a PLL is to clean up a potentially noisy input reference. The transfer function Y/R should thus have as low a bandwidth as possible.

The transfer function from N to Y contains two zeros, both at 0. Because there are no poles at zero, the gain at 0 Hz is 0. As a result, if a constant offset exists in the output of the VCO compared with the command signal, the PLL can always compensate for this offset to produce the correct y(t)=n*r(t). In other words, a gain of 0 means that any dc offset in n(t) is nullified at the output y(t). At very high frequencies, the poles and zeros cancel each other to produce a constant amount of gain from N(s) to Y(s). Thus the PLL cannot nullify high-frequency content in the noise signal N(s), and that high-frequency content passes through to Y(s). Bode plots of Y/R show that the lower the bandwidth of the PLL in Y/R, the lower the frequency at which the PLL can no longer cancel any inherent noise in the VCO. Thus for optimal Y/N performance, it is desirable to have as high a bandwidth as possible.

Comparing the Bode plots of the transfer functions in equations 3 and 4, you can observe the trade-off between rejecting noise in r(t) and rejecting noise in n(t) (Figure 3 and Figure 4). As the bandwidth of Y/R increases, thus allowing more r(t) noise to pass through the circuit, more rejection of higher noise frequencies in n(t) (the Y/N response) simultaneously occurs. The values you choose for R₁, R₂, and C depend on how much noise exists in r(t) compared with n(t). Ideally, you choose the component values such that after combining the noise in all sources, the jitter on the output, y(t), is minimal.

The observed peaking in the Y/R passband in Figure 3, for a particularly low value of R₂, indicates a lower limit for that parameter. Peaking in the frequency domain is undesirable. Communication-system specifications such as SONET specify that jitter-transference curves of nodes in a link must exhibit less than 0.1 dB of peaking, because many such nodes may serially cascade. You can derive similar Bode plots showing the dependence on R₁ and C. In such plots, the bandwidth depends less heavily on C than on R₂, but significant peaking in the frequency response occurs with a low value of C. Because C affects the peaking more extensively than it affects the bandwidth, you can use C during a late-optimization exercise to reduce peaking with little impact on bandwidth.

How well-damped a second-order linear time-invariant system is determines how quick and oscillatory its time response is to a step input. The degree of damping also predicts peaks in the frequency response. Damping in second-order systems arises mathematically within the pole-setting denominator of transfer functions, such as equations 3 and 4. You can rewrite the denominators as follows:

   EQUATION 5

where ξ is the damping factor and ω_n is the natural frequency.

Setting Equation 5 equal to the denominator in Equation 4 yields:

EQUATION 6

How does the damping factor affect performance? Higher damping leads to slower and smoother time response and to less peaking in the frequency domain. Lower damping leads to faster and bouncier time response and more peaking in the frequency domain. For communication systems with PLLs, you must achieve a minimum damping to ensure acceptably low frequency-domain peaking in a plot such as Y/R.

A clear trade-off exists when setting the bandwidth of the PLL. Ideally, the bandwidth will be small, to filter out noise on the reference brought externally into the loop. At the same time, the bandwidth will ideally be large enough to enable the PLL to cancel out VCO noise generated within the loop. Where the optimal bandwidth zone lies depends on the noise quantities in the reference and the VCO. A higher optimal bandwidth applies if the VCO is noisier than the reference source. A lower optimal bandwidth applies if the reference is noisier than the VCO.

You should determine the factor k via the VCO voltage-to-hertz gain and any algorithmic subtleties and the factor n by the expected ratio of the frequency of y(t) to the frequency of r(t). You can initially guess at R₁, R₂, and C using Bode plots of Y/R and Y/N. You also need to determine a reasonable allowable bandwidth for Y/R (for example, 120 kHz maximum for 9.95328-Gbps SONET) and a practical goal for minimum x (such as 3) to achieve a desired Y/R frequency response peak. Additional electrical constraints on the choice of R₁, R₂, and C include dynamic voltage ranges, circuit input- and output-loading capabilities, impedances in the operational amplifier and VCO, and component-size requirements.

Knowing whether the reference source or the VCO will be noisier may also help you. If you know the VCO to be very quiet, then you might be able to achieve a bandwidth far below the specified jitter transfer. Components such as VCXOs that contain high Q characteristics often have excellent low-jitter performance. You could feverishly struggle to obtain the perfect set of parameter values based entirely on transfer functions and noise models. However, because the models will be parametrically imperfect and perhaps even topologically wrong, only testing in the lab with physical parts will truly yield the best final results for this sort of optimization. Hence, after you've determined reasonable component values using analysis and simulation, the next step is to test them in the lab.

The two quantities you want to measure are the jitter on the output clock y(t), and the transfer function, Y/R. You can measure jitter on a spectrum analyzer, which assesses the amount of energy around the main steady-state carrier frequency of y(t). To find the time jitter, add up this energy between certain frequencies around the carrier and compare it with the energy in the carrier. You can think of this fraction, called phase noise, φ_n, in radians, as a fraction of 2π radians (the total radians in one period). The time jitter, then, is φ_n/2πT, where T is the period of the frequency, y(t). Both the noise from the reference and the noise from the VCO affect the time jitter.

You need a more complicated jitter-measurement system to measure Y/R, the jitter transfer versus frequency. Such equipment modulates the reference, r(t), over a band of surrounding frequencies, measures the amount of the modulation frequency at the output, y(t), and compares the two values. You can use several transfer points to construct plots such as those in Figure 3. You should measure the jitter and transfer with a number of parameter-value combinations. Ultimately, a set of plots such as the one shown in the next section reveals the best value set.

A jitter-cleanup circuit often exists in 9.95328-Gbps SONET systems, locking a low-noise VCXO centered around 622.08 MHz to a potentially noisy input clock, also centered at 622.08 MHz. Some SERDES components can accomplish this jitter cleanup by interfacing an internal phase detector to an external VCXO. You can learn more by studying the lab results for a specific implementation with the circuit of Figure 2 controlling a Vectron VCXO JDFCCMUP inside a PLL. The pd(t) phase detected signal comes from a phase detector's comparison between the VCXO output, controlled by c(t), and a potentially noisy input reference clock, r(t). This phase detection occurs inside a SERDES. The SERDES phase-detector interface takes as inputs both y(t) and r(t), and it outputs pd(t).

A laboratory serial-pattern generator supplies a 622.08-MHz, low-noise reference clock, r(t). The pattern generator is part of a bit-error-rate tester that you can configure as a jitter-transfer-curve generator. You can also modulate the pattern generator's clock output in accordance with software that controls the experimental setup. This clock, r(t), is an input to the PLL. After measuring the resulting jitter at y(t), you can generate a jitter-transfer plot by comparing the resulting jitter at y(t) with the jitter forced on the reference, r(t). Jitter-output measurements use the phase-noise-integration utility on a spectrum analyzer. The output, y(t), is nominally a 622.08-MHz signal. After measuring phase noise in a band of frequencies surrounding 622.08 MHz, then integrating this phase noise using the spectrum analyzer, you can determine a final number of radians.

This example measures the jitter transfer and jitter generation of the PLL versus a varying R₂ with an R₁ of 4.32 kΩ. The value of C is 2.2 µF, which aims to avoid peaking in the frequency domain. The goal is to find a value of R₂ for which the jitter is minimal and for which minimal peaking also exists. The SONET specification requires that the transfer Y/R bandwidth must be lower than 120 kHz with peaking of less than 0.1 dB. R₂=14.3 kΩ is the lowest point at which jitter-transfer peaking does not exist and at which the bandwidth is less than 120 kHz. The jitter on y(t) is 0.43 psec rms, using the phase noise integrated from 10 kHz to 20 MHz around the carrier of 622.08 MHz. Any deviation in R₂, whether higher or lower, produces higher measured jitter. Each variation of R₂ results in the construction of corresponding jitter-transfer plots (Figure 5).

Normally, you might expect that based on Equation 6, jitter-transfer peaking increases with decreasing values of R₂. Presumably, again based on Equation 6, even smaller values of R₂—of less than 2.37 kΩ—would result in the appearance of peaking. In Figure 5, though, jitter-transfer peaking increases with higher values of R₂. This increase is one example of why lab experiments are crucial to empirically determine a final set of parameter values. As it turns out, the first-order pole inside the op amp is in the loop filter interacts with the rest of the system dynamics to lower the phase margin in cases of higher resistances and higher bandwidth. The plots in Figure 5 spawn an effort to resimulate and reanalyze the system, to uncover this unforeseen dynamic.

In another example, a SERDES component contains all of the circuits, except for the resistors and capacitors in the loop filter, in a PLL. The op amp, phase detector, and VCO all reside within the SERDES. This configuration provides a simpler bill of materials than a PLL with a phase detector in one chip and a VCO or VCXO in another. Nevertheless, the optimization routine is the same: Vary R₂ and, potentially, C until you optimize the jitter. This case differs from the previous one, in which a standard (SONET) limits the jitter-transfer bandwidth to less than 120 kHz. The main task for this example is to minimize jitter based only on balancing the noise of the VCO with the noise of an external reference. There is no need to further tweak the components to achieve a specified bandwidth.

The plot in Figure 6 demonstrates the trade-off between bandwidths that are too high and those that are too low. With a very low value for R₂, the lower bandwidth restricts the PLL's ability to reject noise from within the VCO. Increasing the value of R₂ and, thus, the bandwidth, lowers the jitter, because the PLL can cancel out more VCO noise at higher frequencies. However, once the value of R₂ is high enough, the larger bandwidth allows so much noise to pass through from the reference that it swamps the improved VCO noise rejection. Lab experimentation determines the minimum jitter you can achieve with a specific value for R₂.