FROM EDN EUROPE: Embed hardware to debug complex FPGAs

You can increase visibility into the operation of a design implemented in a large FPGA from any vendor, such as Xilinx, Altera, Actel, or Lattice, or a mix of these FPGAs, with Temento Systems' Dialite instrumentation. Temento's tools let you create instrumentation blocks that become part of the configuration code for the programmable device. Via a JTAG-port, you can then use the "virtual instruments" to observe activity at the selected nodes, at full operating speed.

You can place the instrumentation IP blocks into your design in a drag-and-drop graphical environment; your functional code (VHDL or Verilog) incorporates the IP and compiles it along with the rest of the design. You can set triggers to watch for serial or parallel events or glitches, set multiconditional triggers (as with a logic analyser), and generate synchronisation signals. Preconfigured IP cores include a traffic analyser that monitors DMA cycles and measures activity or bus occupancy; memory-based history and transaction registers for pre- and post-trigger event capture; and a pseudorandom generator to stimulate buses and check for incorrect activity. The DLI core-control-and-display module routes measured results to an external display. For large FPGA designs, Temento says, the overhead of embedding the instrumentation IP is small—only a few percent. For production, you can recompile the proven design without the instrumentation IP, or you can leave it in place for future development and support. The latest version of the tools, DLI4, is available for all versions of Windows for $2800.

Temento Systems, +33 4 56 52 60 00, www.temento.com.