Managing phase rotation in PLL synthesizers

Many RF systems, especially those related to the telecom market, need reference signals with accurate and stable frequencies. Single-chip PLLs (phase-lock loops), such as those that several IC suppliers provide, have a standard architecture (Reference 1 and Figure 1).

In the charge-pump PLL, the output of the phase detector is a current pulse of fixed amplitude and of a duration equal to the phase difference between its two input signals. After the initial transient, these two signals reach the same frequency, f_COMPARE, and, ideally, the output of the phase detector neither sources nor sinks any current and appears as an infinitely large impedance.

Even as telecom-market growth drives these components' improvement, the behavior of each block is unavoidably nonideal. When you need very high performance, especially in phase noise and stability, you need to evaluate countermeasures to limit the side effects of nonideal behavior. Common unwanted phase-related phenomena are phase jitter, phase wander, phase drift, and phase instability; the first two have a zero average. If the signal is:

EQUATION 1

then

EQUATION 2

This article investigates phase-drift aspects. Because frequency is the time derivative of phase, you can see a quick phase variation due to instability using a spectrum analyzer. In this case, you must revise the loop-filter design to achieve a better phase margin.

Phase drift depends strongly on temperature, so the rate of drift-induced phase variations is normally slow and generates a modest frequency error. Also note that a rotation of the phase of f_IN causes a rotation of the phase of f_OUT. This concept is easily understandable when you consider that the phase detector compensates for each phase difference between the signals f_IN/R and f_OUT/N.

To perform a reliable and accurate measurement, you can use one of two setups in Figure 2. By measuring the delay between the zero crossings of the two signals over time, you can work back to the phase rotation.

Factors that can, in principle, affect the phase of the output signal are different delays between main and reference prescalers; leakage current of the charge pump; impedance of the VCO control port; analog delay of the VCO output amplifier; and delay due to length of the pc-board tracks (Reference 2). All of these parameters cause a static phase shift of the signal. This shift is insignificant in practice, except for few applications or when it is so large, it drives the system into instability. Some of these parameters are temperature-sensitive, so a temperature variation produces a change in the static shift, which is the phase rotation of interest.

The impedance of the VCO-control port plays an important role. Recall how the PLL generates the VCO voltage. The phase detector, I_M, generates the current pulses.

The averaged current over a period of f_REF is:

 EQUATION 3

You can apply this formula only in steady-state mode—not during transient conditions. The loop filter converts the phase-detector output current to a voltage. The simplest and classical form of the filter is the lead-lag network with a pole.

However, instead of focusing on the impedance of the VCO-control port, it is better to refer to a leakage current, I_V. This leakage current is the reverse current of the varactor diode inside the VCO, which is connected between the control port and the ground (Figure 3).

Figure 4 depicts the entire circuit, taking into account the current, I_V, and the current generator inside the PLL charge pump, I_M. Ideally, I_V is zero. Once C₁ and C₂ become charged during the transient period, they remain at that voltage as long as the input and VCO frequencies remain unchanged. In fact, they need not draw any current.

A real VCO, instead, exhibits a small but nonzero I_V. Therefore, the two capacitors discharge during a time that the period 1/(f_REF–Δt_REF) gives, causing the voltage across VCO to decrease. To maintain the correct voltage on the VCO, the charge pump generates the current pulses necessary to compensate the loss of energy caused by I_V. The only way to generate the pulses, however, is to maintain a phase displacement between the two signals at the phase-detector input.

In practice, R₁<<V_VCO/I_V, so you can remove R₂ from the analysis. Also, there is an equivalent capacitor of value C_EQ=C₁+C₂, discharging on I_V during 1/(f_REF–Δt_REF). If C_EQ is not too large, you can charge it to the voltage that a single current pulse requires, and it will have the correct voltage value, V_VCO, decaying at the end of a pulse until a new pulse occurs.

By definition, the output frequency of a PLL remains constant, so the mean voltage at the VCO input port must be constant. Therefore, after a complete cycle of charge-discharge, the capacitors must reach the same voltage as they had before (Figure 5).

The simple linear time dependence is given by:

EQUATION 4

from which you can calculate the average voltage and thus the central frequency of the synthesizer. Because the capacitors' voltage is limited to V_MIN and V_MAX, you have:

EQUATION 5

which simplifies to

EQUATION 6

where time t₁ and t₂ together form the period of the reference frequency:

EQUATION 7

Combining the last two equations, you get:

EQUATION 8

which represents the phase displacement, measured in time units. To specify the phase in degrees, you refer to the frequency, f_O, of the output signal:

EQUATION 9

Because current I₂ is usually negligible with respect to current I₁, you can simplify Equation 9 as:

EQUATION 10

Some representative numbers at a room temperature of 25°C illustrate the situation. Assume f_O=2 GHz, f_REF=100 kHz, I_V=1 nA, and I₀=1 mA. Then, the expected modulus of the static phase rotation is φ=7.2°. The reverse leakage of the diode often strongly depends on temperature. Rewriting Equation 10 to highlight he phase drift due to the change of the temperature from T₁ to T₂°, you get:

EQUATION 11

If the varactor of the previous example can have a reverse current, I₂=100 nA at 70°C, the phase drift is:

 EQUATION 12

In some applications, a phase rotation as large as previously calculated is unacceptable. You can improve some other parameter, as well as the connection between the filter and the VCO, to minimize the phase rotation. Assuming the output frequency is fixed, then Equation 11 shows that you must optimize parameters f_REF and I_O and limit the variation of I_V.

The reference frequency should be as high as possible, compatible with the required channel spacing. Many commercial PLLs let the user select the current, I_O, from two values. (The range usually varies from 500 µA to 4 mA). Users often employ the higher value to speed the settling time of the synthesizer. This speedup could improve the phase-rotation behavior; however, it could also affect the phase noise of the PLL. Some components are optimal, from a noise point of view, with a high current; others are better with a low current. Another side effect is the potential of increased levels of radiated noise when you use the higher current, so carefully make your evaluation.

When you need high stability in a wide temperature range, you may need to decouple the output of the filter from the input of the VCO using a buffer circuit. However, you must carefully design this buffer to avoid degrading the phase-noise performances of the synthesizer. In fact, the decoupling circuitry noise, which the semiconductor junction of the buffer itself generates, is superimposed on the voltage coming from the filter. I_O then applies the noise directly to the VCO control port, causing frequency modulation of the output signal.

You can practically implement the buffers with a simple emitter-follower or a more elaborate op-amp-based filter. Both methods add some noise to the output. The current that the base of the emitter-follower circuit draws is higher than the leakage of the varactor, but it is sometimes more stable with temperature. Therefore, the static offset is higher and the drift is lower than in the unbuffered case. Furthermore, you must be cautious with the voltage drop that the base-emitter junction of the transistor causes.

In most cases, a better approach is to buffer through an op-amp voltage follower or an active filter. The component you choose must have low input bias current and the best possible noise performances. With an op amp, the leakage current can also be positive, so that it can charge, rather than discharge, the capacitors during the t₂ time of Figure 5. Therefore, the phase rotation can occur in the opposite direction from the unbuffered, or emitter-follower, case.

Another concern is that the leakages on the dielectric in the capacitors also affect the current I_V (Reference 3). A high-value resistor in parallel with the capacitor represents these leakages, but, under the steady-state condition, you can calculate an equivalent discharging current to add to the I_V current. The final buffering stage cannot compensate for this problem, because it generates directly inside the capacitor. It is therefore important to choose capacitors with reduced leakage variations over temperature. A typical ceramic NPO capacitor has leakage resistance of about 10,000 GΩ·nF at 0°C, dropping nearly linearly down to about 2000 GΩ·nF at 70°C.

Note that the leakage value depends on both the capacitor value and the temperature. Also, keep in mind that the board itself can cause leakage, so keep it free of solder-paste residue and humidity, both of which make it difficult to predict the temperature-versus-leakage behavior.

As usual, when working at high frequencies, the power-supply rail must be especially clean, free of noise, well-filtered, and decoupled. The ground plane should be large enough to have minimum parasitic inductance and therefore serve as a low-impedance drain for the RF currents. You should properly decouple from the synthesizer areas any digital sections on the same board. Even if it operates mostly at a low frequency, you should keep the loop filter separate from digital areas to avoid picking up radiated noise that the VCO can modulate.