A good fit: Power FETs find their place

Early in the PC's progression into a mass-market consumer product, Intel chose to focus on processor-clock speed as the key indicator of performance. The headline figure in each generation climbed through 90 and 100 MHz, made steady progress through the hundreds of megahertz, and now resides in the gigahertz region. Having made processor speed the performance yardstick, Intel and AMD still keep further pushing speeds, and processor speed remains a significant contributor to PC performance. However, consumers have come to recognize that other factors may contribute more to the overall performance of machines for their specific tasks; a fast disk might speed your application more than an upgrade to a processor with a higher clock speed, for example.

The situation in the PC market is analogous to the recent progress that power-semiconductor manufacturers have made in improving their power-FET switches. As Intel and AMD have headlined megahertz and gigahertz, power-FET manufacturers chose to highlight the minimum value of the channel resistance, or on-resistance, because, a few years ago, the dominant losses in the FETs were I²R losses in conduction. For a given current, cutting on-resistance directly cuts the heat dissipated in the die of the device itself, reducing losses and improving efficiency. Process improvements and new device designs yielded spectacular reductions in these figures with one after another supplier's claiming the "lowest on-resistance in the industry." Suppliers and users multiplied on-resistance by the gate-charge that a given device requires to obtain a figure of merit that served reasonably well for a long time and continues to provide a useful indication of performance. The process continues, but the incremental improvements are getting smaller.

Just as microprocessors have led the way in logic design, they are also a driving force in low-power conversion; point-of-load regulation to feed PC processors must already supply 80 to 90A currents at less than 2V, and you can expect microprocessor-core power demands of 130A at 1V by 2005. These amperages cite peak current demand; even with the exotic heat-sinking that 4-GHz processor chips enjoy, these chips do not continuously dissipate 130W. Large functional blocks on the chips switch on and off as required, and the requirement for very fast transient response in the VRM (voltage-regulator module) is growing. By 2005, you will need to build a regulator that can perform at 400A/µsec to keep a server CPU happy.

Is this information relevant if you are concerned with less demanding applications than leading-edge Pentium or Athlon VRMs? If you simply want to use the latest devices as solid-state switches to control power flow, then it's probably not (see sidebar "Higher integration?"). You can take the devices at face value for their small dimensions and minimal on-resistance ratings. Designers working in handheld- and battery-powered-device design also reap the benefit of the improvements in silicon processing, which now yields almost-ideal switches in packages much smaller than the SO-8 styles at issue here. SO-8 and its derivatives seem to have attracted the greatest recent development effort, perhaps because they represent a sweet-spot combination of high electrical performance with acceptably small board-space requirements. But, although the demands of the latest Pentium represent an extreme case, they are defining the practices that will filter down to other switching and conversion applications. The demands of the VRM and the refinement of synchronous-rectification techniques mean that device and package innovations will first appear in switches rated for lower voltages, but the performance that the VRM achieves will set expectations in other sectors.

So, device manufacturers have greatly reduced the on-resistance of the FET itself. And, they have reduced the board area that the packaged device consumes for a given current-handling capacity, which is also good news. Manufacturers achieve this reduction by combining improved packaging, the ability to accommodate a larger silicon die within the same outline, and a higher current-handling capacity per unit area of silicon. A smaller die tends to go hand in hand with the smaller gate charge required to fully turn on the switch—although no exact relationship exists between the two parameters, and their ratio depends on the individual manufacturer's device geometry.

The fact that the on-resistance has not gone to zero tempers all of this good news; you still need to remove heat from the device, and that heat is now localized in a smaller area than before, complicating the task of transferring it into board or heat sink. From the perspective of a user, power-supply-builder Lambda's technical director, Andy Skinner, dismisses data sheets that quote a rise in die temperature when you mount a given device on a square inch of copper, explaining that the reason he works with these packages and devices in the first place is that he doesn't have that kind of area to play with. In fact, Skinner adds, Lambda never uses the FETs close to their rated current. "Driven by the need for very high efficiency," Skinner notes, Lambda is "exploiting the low R_DS(ON) figures, and the current rating comes almost as a byproduct." Lambda has just introduced the Tarka series of nonisolated dc/dc converters. It uses a four-layer board with heat- and current-spreading copper layers to balance the temperature rise across the whole board (Figure 1).

The SO-8 package size has attracted a lot of recent attention. Although its creators never intended it to serve as a power-device package, the original construction of the SO-8 has changed little from its role as an IC package; the die attached to an internal lead frame with wire-bonded connections, and the entire device was overmolded (Figure 2). You made connections using the package's eight leads, which also served as the primary route via which the devices' heat escaped into the board. A variety of new package formats derive from the same basic outline, all aiming to improve both electrical and thermal conductivity.

The single biggest step toward greater efficiency is improving the thermal contact between die and pc board by removing the molding compound below the lead frame and placing the metal of the lead frame in direct contact with the pc board. The lower surface of the lead frame becomes a large drain contact that you solder to the pc board. It provides a much greater area of metal-to-metal contact to conduct heat away from the board. As a byproduct, it also results in a much lower profile device, because eliminating the molding reduces thickness, and it eliminates the need for you to "jog" the leads down to the board, because the soldering plane is the bottom of the lead frame. A recent product from Vishay Siliconix's PowerPak outline exemplifies this construction. The Si7882DP is an N-channel, low-gate-charge, fast switch for dc/dc converters and similar applications. A gate drive of 2.5V gives an on-resistance of 8 mΩ, and 4.5V gives 5.5 mΩ, for current ratings of 18 and 22A, respectively. (These figures represent equivalent I²R dissipation in the die.) V_DS is 12V. In the PowerPak implementation, the package retains a footprint of 6.5×5.5 mm, but its thickness measures 1.07 mm. The drain contact, which also extends to all four pads on one edge, consumes most of the underside of the package. Three of the four pads on the opposite edge are parallel-connected to the source; the remaining pad is the gate.

STMicroelectronics' data sheets are among those including a set of rule-of-thumb formulas to assess the power-loss performance of pairs of devices in a buck converter. As the notes observe, real device behavior depends highly on how well you remove the heat that the device dissipates. ST is now introducing devices in the third generation of its StripFET technology. Although most of the industry has opted for a trench-based FET construction, ST uses an alternative geometry to achieve the cell densities that yield the performance figures of current devices. In a conventional, leaded SO-8 package, for example, ST's 30V ST25 NH3LL is a 3.5-mΩ-on-resistance part for a 60-nC gate charge. The company has also been developing its own variants of the SO-8 package and others, including the D-Pak. ST's Bondless SO-8 replaces the internal bond wires from lead frame to source with a single copper clip that it solders directly to the die. The PowerSO-8 variant offers an exposed lead frame to conduct heat away from the device. Filippo di Giovanni, power-MOSFET technical-marketing manager, says that after several years of development, ST has eliminated almost all of the on-resistance that the package contributes to the device, lowering it to only 0.2 mΩ. He adds that tests show that ST has also minimized observed losses using these devices in the low-side switch of a converter, where conduction losses dominate. Further reductions in converter losses are becoming "as much art as science," notes di Giovanni, as combinations of various FET parameters plus layout can act to produce, for example, unexpected and lossy voltage spikes.

Hitachi and Philips both use the LF-Pak (Figure 3), which follows similar principles with a drain contact over most of the lower surface of the package and a solid source contact, somewhat like a second lead frame, that attaches to the top of the die by gold "bumps." Hitachi's figures say that this construction cuts channel-to-case thermal resistance from 50 to 3°C/W and approximately halves electrical resistance and inductance versus a standard SO-8. Philips' power-product marketing manager, Ian Moulding, describes this construction as a lead frame that "sandwiches" the die. One of Philips' most popular parts is a FET with an on-resistance rating of 8.2 mΩ; it offers the best balance of gate charge and resistance when you use it as the control FET in a synchronous buck-converter layout. Philips is extending the principles to smaller devices in the range it calls "µ-TrenchMOS." For example, the company is putting copper-lead frames into SOT-23 packages to make low-profile point-of-load converters that will yield 4 to 5A for applications such as low-profile LCD panels and PCMCIA cards. Moulding says that the bond wires in these smaller packages are the limiting factors for performance.

The most radical of SO-8-size package development is International Rectifier's DirectFET, which is an SO-8-family package only in the sense that it is a surface-mount device and fits within the same outline. The DirectFET (Figure 4) uses a small metal can, formed as an inverted dish. On two opposite edges, the sides of the package extend into contact pads, which form the drain connection of the FET; the can is at drain potential. The die attaches directly to the metal of the package. It sits inverted in the package with its source and gate contacts arranged to be coplanar with the drain connections for direct reflow-soldering to the pc board. The drain contact is therefore available at either end of the "bridge" that the package forms. You take the tracks for the source and gate contacts out either side of the package. The height difference between the plane of the solder pads and the side edge of the package is about 0.12 mm, according to IR's Andrew Sawle, director of DirectFET-platform development. When you reflow-solder the package, the clearance between the package edge and the source/drain tracks you run beneath it is around ¼ mm. Sawle confirms that the track needs a well-defined solder mask as it passes under the package side.

The metal can of the DirectFET allows innovative circuit layouts. You can use the length of the can of the low-side transistor as a pc-board "track" with low impedance to connect the high-side transistor and the output inductor to further cut parasitics (Figure 5). In one circuit, this layout alone accounted for a 1% efficiency gain, Sawle says. The use of the term "impedance" is intentional. IR has performed measurements indicating that as switching frequencies rise above 1 MHz, parasitic components and even skin effect start to have a marked effect on regulator and converter performance. Package and pc-board track inductance begins to play a part; IR claims it can address this issue, because the intrinsic inductance for the metal package is extremely low. IR modeled the fundamental electrical parameters—resistance and inductance—of its package design from theoretical principles, confirmed by measurements. Measuring such parameters is a challenging task, because you need to be able to resolve less than 1 nH.

DirectFETs also illustrate a relatively new question for power-circuit designers: How do you prototype with these new packages? With leaded surface-mount packages, you could work with conventional soldering tools to make the lead-to-board connection. The electrical and thermal operation of bottomless-SO-8 style packages and DirectFETs, however, depends on good bonds between the pads on the device underside and the corresponding pads on the pc board. Such bonds call for reflow-solder joints, and the minimum level of equipment is a hot-air spot-action reflow "gun." IR has created miniature one-time stencils to lay down the correct pad pattern of solder paste to attach a single direct-FET device. With a one-time single-device stencil, you apply solder paste with a miniature spatula, remove the stencil, position the FET with tweezers or a micromanipulator, preheat the pc board, and apply hot air to the device to reflow the solder.

All of this attention on improving the performance of conduction of heat into the board assumes that you want it there in the first place. Increasingly, however, you may have nearby components already dumping more than enough heat into the board, and the only significant areas of copper available might be internal layers. With metal-can devices, you can draw off some heat from the top surface by forced air, thermally conductive gel mat, or even heat pipe. These measures also work with the molded variants, although, because they still have epoxy between die and top surface, this approach is less effective.

In any event, because the losses that the semiconductor switches contribute approach minimum values that may be tough to improve, you need to direct attention to more efficient design of, for example, magnetic components, to further cut losses.

LFPak, PowerPak, DirectFET, and other packages house devices whose data sheets quote on-resistance figures of as little as 2 to 3 mΩ. You therefore need to ensure that your connections to and around the packages are of similar low resistance, or the conduction losses in the interconnection will dwarf the conduction losses in the FET itself. One-ounce copper foil on a pc board has a resistivity of about 0.5 mΩ/sq in. FET manufacturers provide small devices, and naturally you want to use the board area that these devices free by packing in surrounding components. If you can find room to route, say, a 2-mm-wide track to the source or drain connection of your switch, a mere 8-mm length of such a track offers the same resistance as the FET itself. The need for maximum copper area, short tracks, and sound interconnections is clear. You may need to consider using a heavier weight of copper on at least one of the pc-board layers, and high current via design can be critical for areas in which you need to transfer high current, thermal connection, or both between layers.

Key parameters, such as the ratio of gate/source to gate/drain capacitance, can affect efficiency. Each pair of devices for use in a switching converter and even each layout can exhibit its own second-order behavior. None of these phenomena mattered much when you could make large gains in overall efficiency by using the latest generation FETs for lower conduction losses, but where should you now be looking for lower losses?

Because conduction losses dominate in the low-side switch, and you must look for reduced switching losses in the high-side switch. At Fairchild, packaging specialist John Bendel focuses attention on the importance of the reverse recovery time of the low-side FET. The buck circuit demands a certain off-time or dead time between the "on" periods of the two switches. Adaptive dead-time controllers set this parameter, and most designs have now trimmed it to the bare minimum. For the low-side switch, Fairchild proposes its SyncFET, which is a trench MOSFET, with a Schottky diode structure (actually a "graded drain-trench MOS-barrier Schottky"). In the SyncFET, Fairchild fabricates the FET and the diode together at the level of each cell of the device, giving the device a very fast recovery time at the expense of a somewhat reduced on-resistance. (The design allocates to the Schottky some of the silicon area that FET trenches would otherwise use.) According to Fairchild's analysis, this design can produce a counterintuitive result, indicating that, in some circumstances, using a higher on-resistance part in the low side (where conduction losses are supposed to dominate) produces lower overall losses. The reasoning is that, with minimum dead time, a high-side switch that turns on before the low side has recovered after switching off (via the FET's intrinsic diode or an external Schottky), is in effect turning on into a short. This situation constitutes a short spike of the very shoot-through current that the switching dead time aims to avoid. The energy appears as extra heating of the high-side switch. Bendel suggests that you might see this effect more when your output voltage is a small fraction of the input; you might also see it when switching frequencies rise, causing the parasitic inductances around the FET/Schottky pair to slow the recovery current. This type of phenomenon is, he adds, extremely difficult to measure. In a demonstration, Fairchild carried out an analysis entirely in Spice and confirmed the simulation by thermal imaging of the pc board. Substituting a 7-mΩ SyncFET for a regular 4.2-mΩ FET plus external Schottky in a regulator producing 1.25V from 19V at 12A increased efficiency by 1%, and the thermal image confirmed that the high-side FET was indeed cooler.

Lambda's Skinner confirms the value of thermal-imaging cameras in tracking down the diminishing fractions of a percent that make the difference in overall efficiency, calling the tools "completely indispensable." (See www.flirthermography.com for examples.) As the on-resistance race tails off into ever-smaller incremental gains, you will have to run more and more techniques, such as thermal imaging, to identify the second-order effects and subtle interactions of parasitic components as they sap the efficiency of your designs.

Author Information

You can reach Editor Graham Prophet at +44 118 935 1650, fax +44 118 935 1670, e-mail gprophet@reedbusiness.com.