CompactPCI vendors are just now beginning to extend their technology for future products after being stopped in their tracks by the recent economic downturn in the telecommunications industry. Board manufacturers are pushing the technology envelope with new standards for high-speed interconnects along with improved reliability, manageability, and serviceability. They hope to expand the market for off-the-shelf, carrier-grade telecommunications equipment while extending their reach into new applications. With new customers demanding higher bandwidth systems with very little downtime, CompactPCI developers are updating the specification for their next-generation systems, and several of these updates include replacement of CompactPCI's namesake, the PCI bus, with higher speed, nonblocking alternatives.

The PICMG (PCI Industrial Computer Manufacturers Group) introduced CompactPCI at the height of the telecommunications boom with the goal of packaging low-cost, desktop hardware in a rugged form factor. This scheme gave developers access to off-the-shelf PCI silicon and readily available desktop-software applications. CompactPCI is an open specification that PICMG supports and controls. You can download a short-form version of the specification at www.picmg.org. PICMG based CompactPCI boards on the Eurocard industry standard defining both 3U (100×160-mm) and 6U (233.35×160-mm) boards. The more popular 6U version has as many as five connectors on the rear of the card, allocating two for the CompactPCI bus; the remaining three optionally provide 315 pins for user-defined I/O connections. Each CompactPCI bus segment consists of one system slot and as many as seven peripheral slots. The system-slot board provides arbitration, clock distribution, and reset functions for all boards in the segment. The peripheral slots may contain simple PCI boards, intelligent slaves, or PCI-bus masters.

As data rates rise, systems built on CompactPCI technology are beginning to feel the performance limitations of the PCI bus. Efforts to increase the 33-MHz PCI-bus clock rate have created other problems. The eight-board bus segment shrinks to four slots at 66 MHz and only one slot at 133 MHz. Although CompactPCI vendors have used PCI-to-PCI bridge technology to address the slot limitations, these bridges introduce unacceptable latency issues in some applications. High-availability advocates question the entire concept of a shared bus in which a single failure can potentially lock up or disable all boards on the bus.

To keep up with user demands, PICMG initiated a series of CompactPCI 2.x specifications to improve performance in diverse industry segments. For example, telecommunications customers needed hot-swap capability to replace defective boards without shutting down their systems. Hot-swap systems require hardware and software that can dynamically route signals around defective components while waiting for repairs. Other new specifications standardized backplane signals for instrumentation, computer telephony, management, and backup buses.

PICMG 2.16, one of the most recent additions to the family of specifications, adds a packet-based switching architecture on top of CompactPCI. The standard defines an Ethernet-based, dual-star system-area network between boards within a CompactPCI chassis. Also called CompactPCI PSB (packet-switching backplane), PICMG 2.16 increases the interboard communication bandwidth by moving data off the shared PCI bus onto a high-speed, switched 10/100/1000-Mbps Ethernet-based network. Users can improve throughput by as much as an order of magnitude without affecting legacy components or the shared CompactPCI bus. You access the Ethernet system via the J3 connector, and boards communicate with each other through a conventional network stack. Users can construct a large virtual backplane by extending the network to other chassis with a simple Ethernet cable. With 95% of worldwide data traveling on Ethernet, PICMG 2.16 developers have an ample supply of interface hardware and software.

The PP 120/01x from Concurrent Technologies supports several of the PICMG specifications, including 2.16 for backplane Ethernet (Figure 1). The low-power, dual-Pentium III, single-slot PP 120/01x CompactPCI board supports four individual Gigabit Ethernet channels. Each of the two 933-MHz processors supports a 133-MHz front-side bus with 512 kbytes of L2 cache. The board also features as much as 1 Gbyte of 133-MHz ECC SDRAM, an Ultra 160 SCSI interface, and a 64-bit, 66-MHz PMC site. The board can operate in a system-control slot or in a peripheral slot with the CompactPCI interface disabled. The PP 120/01x also features an EIDE (enhanced integrated-drive-electronics) interface with installed options for an onboard 2.5-inch disk drive or a Compact-Flash carrier. For increased reliability, heat sinks—not fans—cool the two CPUs. Other features available are a PC real-time clock, a floppy-disk interface, two RS-232 channels, two USB ports, a parallel printer port, a watchdog timer, a keyboard/mouse interface, a long-duration timer, and a graphics interface. The PP 120/01x supports Linux, Windows, and QNX operating systems. Prices start at $2988 (high volumes).

General Micro Systems also has a line of CompactPCI boards complying with the 2.x series of PICMG specifications. Two low-power Pentium IV Xeon processors, each with 512 kbytes of L2 Cache and CPU clock speeds initially fixed at 1.6 GHz but expected to exceed 3 GHz power the C269 Equinox (Figure 2). The Equinox uses a unique four-port hub technology for memory and I/O transfers to take full advantage of the CPU performance. The board routes dual Gigabit Ethernet channels to the rear I/O pins to support PICMG 2.16 channel A and B or for access on the rear-transition I/O- module device. An Ultra SCSI-320 interface can support maximum transfer rates of 320 Mbytes/sec in single-ended or differential modes. One port of the internal hub provides a 4-Gbyte/sec I/O-expansion bus for custom external interfaces. The Equinox provides standard interfaces, such as two COM ports and interfaces for a floppy disk, a real-time clock, CMOS RAM, a keyboard, and a mouse, along with two Ultra DMA-133 IDE channels to provide the user with hard-drive, CD-ROM, and flash storage options. The board derives all CPU core-power requirements from an onboard dc/dc converter, which an external 12V supply powers. It requires no additional power source except for the standard CompactPCI 3.3 and 5V supplies. Single-piece prices for the C269 start at $2400. The board supports Windows NT/2000, Solaris x86, VxWorks, QNX, and Linux operating systems.

Even further pushing the data bandwidth, PICMG 2.17 implements StarFabric technology within a standard CompactPCI chassis. Users may choose to replace any number of CompactPCI slots in a system with StarFabric to obtain a higher speed point-to-point interconnect and retain compatibility with earlier PICMG specifications. As with PICMG 2.16, users may also interconnect multiple chassis to create a large virtual backplane. PICMG 2.17 defines both centralized and distributed topologies (Figure 3). The centralized topology includes one or two fabric boards that interconnect all the slots in the chassis. This arrangement allows redundant fabrics for large-scale systems. A distributed topology has the switching capability integrated on each slot board and requires no separate switch card. This architecture provides a method for interconnecting cards in smaller systems without using valuable slots for dedicated switching elements.

Aurora Technologies offers a StarFabric development kit for designers interested in a quick start in PICMG 2.17 development (Figure 4). The kit integrates Aurora's CP-SFX8 Fabric Card with an eight-slot, 2.17-compliant backplane and a portable aluminum enclosure. The CP-SFX8 6U fabric card lets you implement a centralized fabric topology in a CompactPCI chassis. The Fabric Card features eight links to the backplane with a switching bandwidth of 5 Gbps per port, two front-panel links for connection to a redundant external chassis, and Microsoft Windows or Linux compatibility. The kit includes CG Mupac's 9U portable enclosure, which accommodates eight 6U×160-mm CompactPCI boards. The backplane supports the system-management bus as specified in PICMG 2.9, 5 or 3.3V keying, and hot-swap capabiltity. Prices for the StarFabric development kit start at $4900.

Continuing with another high-speed serial-fabric architecture, PICMG 2.20 defines a serial-mesh backplane to enable cell-based data transport for CompactPCI platforms. In a mesh architecture, each slot has a direct path to every other slot without an intervening switch or router card. The serial-mesh-backplane architecture can increase data-transport capacities to as much as 700 Gbps and supports multiple simultaneous protocols, such as ATM, IP, Frame Relay, GPRS Tunneling Protocol, and others. Motorola Computer Group has launched the MXP3321 platform to conform with the 2.20 serial-mesh-backplane specification (Figure 5). The MXP3321 targets multiservice-switching applications, such as multiprotocol routers, 3G wireless-radio-network controllers, and media gateways. Because the communication between any two slots does not depend on what protocols may exist elsewhere in the platform, you can easily adapt this architecture to fit many applications. The MXP-platform products rely on Altera Mercury devices to provide the high-speed link that the serial-mesh backplane uses.

Unfortunately, most of the CompactPCI addendums are optional and have saddled board vendors with a mishmash of specifications that threaten to fragment the industry. Boards from one manufacturer conforming to some of the 2.x specifications may not work in the same chassis with boards developed under a different set of specifications. CompactPCI developers have also complained of inadequate board area and cooling problems with the standard 6U boards and chassis. These problems, along with the limitations of the PCI bus, led a group of PICMG member companies to step back and develop a new platform optimized for high-speed, communications applications. This new platform specification, AdvancedTCA (Advanced Telecom Computing Architecture), describes a larger form factor, eliminates the parallel bus, and includes a mesh backplane (see sidebar "AdvancedTCA: another direction").

Some board manufacturers feel that the current CompactPCI architecture can adapt to future needs by including PICMG 2.16 packet switching as the primary interconnection, requiring mandatory system management and eliminating the PCI bus for data transfer. Force Computers, Motorola Computer Group, Performance Technologies, Pigeon Point Systems, StarGen, and Znyx Networks are expected to soon introduce the Telecommunications Computing Architecture, or CompactTCA, as a new PICMG. CompactTCA specification authors hope to retain compatibility with PICMG 2.16 products while combining several optional specifications into a single standard.

The new and proposed PICMG specifications—such as PICMG 2.16, AdvancedTCA, and CompactTCA—are industry reactions to the limitations of parallel, shared bus architectures. These new specifications feature serial networks and fabrics that allow multiple data streams to move at the same time, along with new techniques for system management. The advantages of these new specifications are that they are nonproprietary and that dozens of leading board manufacturers support them. Although the future direction of CompactPCI is unclear, it will probably not include the PCI bus.

Author Information

You can reach Technical Editor Warren Webb at 1-858-513-3713, fax 1-858-486-3646, e-mail wwebb@edn.com.