Computers find universal use in industrial-control systems. During power- and start-up sequences (booting), the outputs of such control systems may yield uncontrolled pulses before the software defines the correct status. If these outputs control the power-on state of a system, these uncontrolled pulses could have dramatic consequences. Safety regulations forbid such erratic behavior. The circuit in Figure 1 is a cost-effective approach to the spurious-pulse problem. The circuit costs approximately 10 times less than other available timers. The open-collector output of the controlling device connects to the reset input of the CD4060 counter, IC₁. You can easily adapt this circuit to other controller-output configurations, such as an optocoupler. As long as R₁ pulls the reset input high (controller-output off), the counter's clock stays disabled and all outputs are low. C, R₂, and R₃ are the timing components for IC₁. With R₂=R₃=10 kΩ and C=0.1 µF, the measured clock frequency is approximately 360 Hz.

The output of the circuit is Q12. The reset input must stay low longer than T=(2^n–1)/f=(2048)/360=5 sec for the output to turn on (n is the output number, 12). Any spurious pulse from the controller's output that is shorter than 5 sec has no effect on the output of the circuit. Output Q13 of the counter turns on after 11 sec, Q14 after 23 sec, and so on. The LED, connected to Q7 through R₄, flashes during the timing period. With V_CC=12V and an LED current of 10 mA, R₄=(V_CC–2)/10=1 kΩ. For safety reasons, you can add the optocoupler, IC₂. If output Q12 of the counter fails (shorted to V_CC), the output turns on only if the controller's output is on. Choose the value of R₁ depending on the controller's output and the noise level; in this design, R₁=10 kΩ. Note that V_CC should have a maximum value of 15V for the CD4060 and 6V for the 74HC4060.

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