Formal verification gets an upgrade

Version 4.0 of Real Intent's Verix tool targets the formal-verification market, which has been growing in the last couple of years as more companies adopt the approach to improve or speed verification cycles for complex designs. The new version provides assertion checks for finite-state machines by extracting the state machines from the RTL code and then applying the assertion checks to prove the correct operation of the resulting hardware. The checks ensure that the tool can reach all states, that no single-state or pairwise state deadlock exists, and that none of the state-vector bits are stuck.

The product also has an enhanced clock-intent verification to ensure the stability and accuracy of data transfers between clock domains. Verix can detect the absence of synchronizers, glitch potentials, flop resets from asynchronous domains, and other types of bugs common in asynchronous designs. Verix also supports the OVL (Open Verification Library) standard from Accellera (www.accellera.com), so designers can now apply formal analysis to verify behaviors expressed in OVL. Prices for Verix 4.0 start at $60,000. The product is available for Solaris, HP-UX, and Linux platforms and supports Verilog and VHDL design languages.

Real Intent, 1-408-982-5444, www.realintent.com.