FROM EDN EUROPE: FPGAs among first to use 90-nm technology

Spartan is Xilinx's leading-edge but cost-reduced FPGA device family. It lacks some of the advanced features of the Virtex family but is optimised for maximum-gate-count-per-unit silicon area and for volume-production economics. In its Spartan-3 series, Xilinx has moved to a 90-nm process to build 50,000-gate to 5 million-gate parts at, the company says, a new low point measured by gates-per-unit cost. If you are ordering at the 250,000-unit level, you will be able to buy a 4 million-gate part for less than $100. This process, Xilinx believes, will allow FPGAs to further penetrate the ASIC market.

The first products—a 50,000-gate part for $3.50 (250,000), and a 1 million-gate part for $20 (250,000)—are available now, but the prices are for volume deliveries in 2004.

In addition to the increased density, Spartan-3 parts acquire the controlled-impedance I/O facility from the Virtex line, allowing signal-path-impedance matching without external components and saving area and cost on high-speed boards by eliminating matching and termination components. They also offer an increased ratio of memory to logic—in both distributed and block memory—over the Spartan-2 series parts.

Xilinx has ported its IP (intellectual-property) libraries to the new devices, and a PCI 32-bit, 33-MHz block will now cost as little as 75 cents, according to the company, depending on the silicon area it consumes. (The company derives this figure from the proportion of the silicon area of a volume-production part that the IP block consumes.) Xilinx has also scaled up the on-chip DSP features with more hardware 18×18-bit multipliers. You can design at system level in Mathworks (www.mathworks.com) software (using a Matlab/Simulink path), and a system-generator package translates your algorithms to efficiently use the on-chip hardware.

Xilinx, +44 870 7350 600, www.xilinx.com.