Target practice

With the electronics industry still on the down slope of the Matterhorn ride, it's fitting that the 40th annual DAC (Design Automation Conference)—which will take place June 2 to 6 at the Anaheim Convention Center—is happening just a few hundred yards from Disneyland. The industry is hoping the ride will soon come to an end, and calmer, more predictable times will follow. The EDA industry in 2002 recorded its first-ever year-to-year sales decline. Total revenues for 2002 were 7% less than 2001, amounting to only $3.7 billion. The good news is that the EDA industry achieved better results than did the semiconductor industry. Unfortunately, EDA customers are either members or customers of the semiconductor industry. So, DAC will face the challenge of attracting attendees in a period of negative growth and with an uncertain outlook for the general economy.

As usual, the DAC program offers something for every IC-design engineer: panel discussions, papers, new products, workshops, and tutorials. Ian Getreu, this year's general chair, says that his goal is to ensure that DAC delivers the most up-to-date program content that engineers can apply to current design challenges. Engineers that design ICs, especially those using custom-design techniques, will find a rich technical program. The conference's emphasis on IC design has an unfortunate side effect, though. Although decrying declining attendance, DAC has once again failed to dedicate any technical sessions to pc-board design, thus failing to provide any incentive for a large number of design professionals to attend the conference.

The conference is also limiting the portion of the program dedicated to exploring design problems with FPGAs to just two sessions that will deal with reconfigurable designs. Yet both pc-board and reconfigurable designs face significant design challenges.

The program includes 54 technical sessions, 22 of which deal with physical-design issues, such as power management, timing-oriented placement, noise avoidance, and interconnect modeling. The program dedicates 19 more sessions to design verification and system-level design. The topics cover subjects from embedded-system design, to self-test, to formal verification methods. Their aim is to show designers how to avoid or detect design errors and fix them in the most efficient way possible. Only three sessions address analog-or mixed-signal design, despite such designs' becoming more prevalent.

Exhibitors are targeting a wider audience than are the technical sessions. FPGA and pc-board designers will be able to see the latest products available and to discuss, especially in the exhibitors' suites, the most pressing problems facing them and the technology under development. Arguably the most important workshop, one that has grown in attendance and visibility every year since its inception, is the WWINDA (Workshop for Women in Design Automation; see sidebar "Tackling career growth").

The EDA industry plays a pivotal role in fostering the growth of the electronics industry. DAC attendees are likely to find some indicators of trends and progress in key areas of electronics design. The capabilities of semiconductor manufacturing are once again outpacing the abilities of designers and the power of EDA tools. State-of-the-art devices are now fabricated with 90-nm technologies, but most designers are still learning to design at 180 nm, and leading-edge EDA tools are struggling to address the problems at 130 nm and smaller. The fundamental issues facing designers and EDA-tool developers are the size of the design, the physical effects predominant at 180 nm and smaller, and the mixed nature of designs that incorporate digital and analog hardware as well as large software modules. There are at least two measures of engineer productivity: the on-time release of a product to manufacturing and the percentage of gates the die uses. The first indicator measures a company's ability to meet the market window for a product, thus optimizing its revenues. The second indicates cost efficiency.

If a company employs a costlier process to produce a die that sees only partially use when a previous-generation process would have sufficed, its corporate profit margin decreases accordingly. The average gate usage at the 130-nm process node is less than 60%, indicating that design teams are not using the available gates at their optimum potential. Texas Instruments, for example, has found that educating design teams about the realities of designing with advanced process technologies increases productivity. Although some of the blame for this lack of education rests with an academic system that graduates too many logic designers and not enough electrical engineers, EDA tools are also falling short of their required capability. In addition, the mask-making industry is about 10 years behind the development of processes by semiconductor foundries in process control, cleaning, inspection, and handling repairs. Although mask suppliers are closely linked with semiconductor fabs, many of the yield-enhancing techniques fabs use have yet to make their way into most mask shops, according to Kurt Kimmel, mask-program director at International Sematech.

The electronics industry traditionally encouraged semiconductor companies to emphasize process development, believing that putting more transistors on a die would lead to more powerful electronic products and thus greater profits. Historically, process capabilities preceded design capabilities by only a year or so, and the bulk of designers were able to use the process within two or three years of its introduction. But the story is different today. Most designers are still using either 250- or 180-nm processes, but semiconductor companies have released 90-nm process and are working on 65 nm. Although a few leading-edge designs are slated to use the latest processes, most of the design industry is at least two processes behind, and the volume-manufacturing capability is also lagging. The time might have come to shift emphasis from the number of transistors on a die to the manufacturability of the die. EDA companies seem to be addressing this point. The tens of millions of available gates on a die lead to design complexity that is beyond the average engineer's ability, and the size of transistors and interconnects are the source of new classes of design problems once confined to second- or third-order importance.

Design verification is the most serious problem facing engineers. The average cost of verification has risen to 70% of the total cost of a project. Because a significant portion of this cost is pure overhead, its impact on the development cost of each product is significant. Contributing most to the high cost of verification are design size, the need to employ both digital and analog techniques, and the significant amount of embedded software in most products. Unfortunately for engineers, the industry has done little in the area of mixed-signals designs.

Digital designers and analog designers use different tools. Digital designers focus on the algorithms to implement. They think of logic in terms of logic states, not in electrical terms. Analog designers, on the other hand, must deal with the physics of electrical systems; they worry about the production of logic states and often how those states translate into analog impulses that humans recognize, as in the case of communication systems. Digital designers have for almost 20 years been using HDLs (hardware-description languages); the use of analog HDLs is barely starting.

Most analog designers still use schematics to enter the description of a circuit into a CAE system. Logic designers look at a circuit in the time domain, and sequential changes in the circuit represent the functions. Analog designers must also deal with the frequency domain and look at signal phases and a host of physical characteristics to effect the required changes at the right time. As a result, the CAE tools that digital designers use rarely interface with the tools analog engineers use, making it more difficult not only to communicate problems, but also to debug systems. The analog block is a black box to the digital designer, and analog engineers must deal with digital signals as given entities. To address this problem, Cadence has introduced the Incisive Verification platform, which supports both digital and analog HDLs and provides a common user interface regardless of design discipline. Mentor offers SystemVision, a simulation environment that bridges math-based modeling with digital-and mixed-signal models by supporting VHDL-AMS, as well as VHDL and Verilog.

The industry has talked for many years about tools for a methodology that Gary Smith, chief analyst for the EDA worldwide program in Gartner Dataquest's Technical Software Group, labels ESL (electronic-system-level) design. The methodology has so far been unsuccessful, as tools have fallen short of their marks. During DVCon in February 2003, Aart de Geus, chairman and chief executive officer of Synopsys, introduced the concept of design for verification. Because verification is so costly, users might receive ESL tools well if they target verification instead of integration or architectural exploration. With the acquisition of Avanti and Co-Design, Synopsys now offers a strong inventory of simulation products that it must still integrate into a multidiscipline platform. The company has declared its full support for System Verilog, a natural evolution of Co-Design's Superlog.

Three years ago, some EDA companies began a marketing effort directed at convincing design engineers that a dialect of C is the most suitable language for describing systems at a higher level of abstraction. In practice, for many years, designers of communication systems have used C to test algorithms that they would then implement using Verilog or VHDL. Bell Labs experimented with using C as an HDL in the early 1990s but eventually abandoned the method. In practice, C and its derivatives are unsuitable languages for hardware design and hold no characteristics that differentiate them from VHDL or improved versions of Verilog, such as System Verilog and Superlog. John Sanguinetti, PhD, chief technology officer of Forte Design Systems, believes that only a C-based language offers the constructs and extensibility that higher level design requires. He believes that Verilog, VHDL, System Verilog, and Java are too implementation-specific and not extensible enough to fill system-level-design requirements. This point of view fails to recognize the facts that System Verilog is an extension of Verilog and that both VHDL and VHDL-AMS, an extension of VHDL, offer most of C's capabilities, including math-based modeling.

Much technical confusion still remains about SystemC. A recent article claims that, "using the same language also makes it possible to simulate the entire system within a single engine" (Reference 1). Yet, the same article describes a circuit simulated using a number of engines. At least one application-specific ISS (instruction-set simulator) executes in conjunction with the SystemC simulator to support microprocessor cores. The same example loses the advantages of a single engine and a single debugging environment, which should illustrate the advantages of SystemC. In most discussions about SystemC, marketing overpowers engineering. Until de Geus announced that Synopsys would fully support System Verilog, that company had been the strongest supporter of SystemC. Although Synopsys will not immediately pull away from SystemC, its development efforts in the area of synthesis support will focus on System Verilog. If synthesis of SystemC design description is weak or left only to small companies, the language will not be a viable tool for system-level design in spite of the marketing efforts.

Design verification based on formal methods is winning recognition as a viable tool to improve designer productivity and design quality. DAC attendees will be able to see new versions of formal-verification products, as well as the integration of formal methods with logic simulation and emulation. Real Intent will show Verix 4.0 at DAC, and 0-In Design Automation has added a PCI Express monitor to its inventory of CheckerWare intellectual property. Datapath design verification has been a challenging problem for formal-verification tools. EDA vendors have incorporated datapath capability into standard synthesis tools, further complicating formal verification. Verplex Systems' new Conformal Datapath verifies the optimized datapath circuitry that high-performance datapath and synthesis tools produce.

The physics of 130- and 90-nm processes have brought to the forefront what were previously noise-level effects. Design closure is a process designers follow to ensure that the physical effects on a die do not interfere with a product's ability to meet its functional requirements. The most common examples include reliability effects, such as signal electromigration, power electromigration, and IR drop; crosstalk glitch; and crosstalk delay. One of the less common problems is managing the process variation inherent in process technologies with feature dimensions that you measure in molecules. Beginning with the 180-nm process, second- and third-order physics effects have become first-order effects. Some of these effects have progressed through the typical EDA-tool life cycle of detection, correction, and prevention—especially in the area of parasitic extraction, which has moved from 2- to 3-D extraction to comprehend effects such as nonlinear resistance, process bias, metal fill, and resistance extraction for vias, contact, gate, and others.

EDA companies must develop and improve tools to support design for manufacturing. ASIC vendors, such as TI, are demonstrating the processes necessary to handle this task. Wherever possible, TI characterizes the library cells to include process- or cell-specific variation effects. For analog cells, such as sense amplifiers, PLLs, and I/Os, this method means using statistical simulation of use scenarios. For digital cells, it means characterizing with accurate Spice models to take into account variation effects, such as negative-bias process instability. At the design level, rather than allowing for the conventional 10% setup margin that was sufficient at 250 nm and larger, TI has developed tools that gather design-specific information and actually calculate the amount of setup-and-hold margin necessary to meet the customer's requirements, given statistical analysis of variation. At multiple stages, the design process calculates and reviews the information.

The various IC-design steps use a number of EDA tools, and the design itself goes through a number of transformations—from behavioral, to register-transfer level, to gate representation. It is imperative that all of these EDA tools be able to interface with each other, not just to provide meaningful data downstream, but also to provide feedback to upstream tools. Because the EDA industry tends to grow from start-ups that specialize in single-point tools, it needs standard interfaces, especially because Cadence and Synopsys own the design flow. Cadence, in collaboration with SI2 (Silicon Integration Initiative) has provided an open API to the OpenAccess design database and is working toward developing an industry standard. It has formed the OAC (OpenAccess Coalition) to facilitate working with other companies, including other EDA vendors. Synopsys, in late 2002, joined the OAC's Golden Gate Working Group, which includes representatives from Hewlett-Packard, IBM, Intel, and Motorola, as well as EDA vendors.

OAC aims to develop an interface between OpenAccess and Milkyway, the Synopsys design database. In February 2003, Synopsys introduced the Galaxy design platform, which provides open access to the Milkyway database and targets design at 130 nm and smaller. Rajeev Madhavan, chief executive officer and chairman of Magma Design Automation, holds a different point of view. He believes that designers and the EDA industry need not just an open database, but an open data model. Both IBM and Honeywell 30 years ago employed the concept of a data model known to all applications in their respective internal CAE systems. After all, an API alone does not necessarily give you the semantics of the data on disk, so errors can still occur when two tools interpret the data differently. With an open-design model, both the syntax and the semantics of the data are commonly available, and all of the tools understand them. BindKey Technologies and Cadence provide one example of successful cooperation. BindKey's RapiDesignClean product executes in tandem with Cadence's Virtuoso layout editor (Figure 1). Layout designers can see the impact of design rules on the choices they make during placement and routing. Engineers receive visual feedback that includes violations as well as hints and notifications every time they select a polygon for placement.

Power-analysis and signal-integrity characterization products will make strong showings at DAC. Chip Vision will show Orinoco, a power-analysis tool that engineers can use to predict power requirements early in the design cycle before they invoke synthesis. The Orinoco power-estimation and -optimization tool suite targets designs that require low power, such as those in all portable devices. Sequence Design offers CoolTime to analyze the electrical effects of power, voltage drop, timing, and signal integrity. Both tools would be even more useful if they were in the same design database as synthesis and place-and-route tools; the results of the analysis would be available concurrently, and you could make design choices without sequentially executing two programs. Sequential execution runs the risk that, in fixing one problem, designers generate another or uncover one that the first problem masked. This method of design takes significantly more time than one in which both tools execute concurrently. ReShape Inc has taken a different approach to improving designer productivity. Instead of developing a new tool, it is packaging a methodology that it has used in many SOC (system-on-chip) designs, offering customers scripts and engineering methods that have proved to increase productivity. Engineers can use this product, called GDS Builder, with both Synopsys and Cadence physical-design tools.

Dynamic-timing analysis is accurate, but it relies on large numbers of simulation vectors to verify circuit performance. Engineers must develop the vectors—a task that is both difficult and time-consuming. Static-timing analysis eliminates the need for simulation vectors but it can lead to wasted effort because designers investigate problems reported on false paths that do not execute in actual applications. Also, static-timing analysis cannot account for the impact on timing of dynamic nanometer effects, such as crosstalk. Nassda Corp has introduced Hanex, a circuit-level timing- and crosstalk-analysis tools for digital designs targeting 130 nm and smaller. It uses hybrid analysis methods to find critical paths in combinatorial, latch/flip-flop, and dynamic logic. The tool simultaneously simulates the entire critical path, considering voltage-dependent capacitance, Miller capacitance, and nonlinear input slopes.

The creativity of EDA engineers is not diminishing, but the complexity of design problems is increasing even more rapidly. Although manufacturers continue to develop point tools, the integrated design flow is still missing, and you will not find it at this year's DAC.

You can reach Technical Editor Gabe Moretti at 1-941-497-9880, fax 1-941-497-9887, e-mail gmoretti@edn.com.