Circuit provides leading-edge blanking

In isolated switch-mode power supplies using peak-current-mode control, generally the current-sense resistor senses the current on the primary side of the power converter. Figure 1 shows a typical circuit, in which R₂ is the current-sense resistor that monitors the current. The current-sense signal goes to the input of the PWM comparator—in this case, the PWM comparator's input (I_SENSE) of the controller IC. R₃ and C₁ provide an RC delay in an attempt to remove some of the leading-edge spikes on the current-sense signal. Sometimes, the RC delay circuit is insufficient for removing the false noise signals at the input of the PWM comparator. This Design Idea shows how to suppress the false triggering signals caused by parasitic LC (inductance and capacitance), causing LC tanking and false-peak current triggering to the peak-current-limit comparator.

The RC delay circuit in Figure 1 works for most applications in suppressing voltage spikes that may falsely trip the peak-limit-current comparator. However, some applications require a leading-edge blanking circuit to suppress false triggering. Figure 2 shows the typical current-sense signal that appears across R₂. The leading-edge spike at time T₁ occurs when the gate drive switches from low to high and the parasitic capacitance from the gate to the source of Q₁ is charging. Depending on the values of R₁ and R₂, a large-enough leading-edge voltage spike could falsely trigger the PWM comparator at the I_SENSE pin. This problem is common in isolated dc/dc power converters. To remove false triggering from the PWM comparator, it is desirable to blank out the leading-edge spikes that appear on the current-sense signal. You can suppress these leading-edge spikes by adding four additional components to the circuit in Figure 1. Figure 3 shows the extra circuitry necessary to provide leading-edge blanking. The gate drive from the PWM circuit activates the leading-edge blanking circuit. Transistor Q₂ suppresses the leading-edge current-signal spike. Components R₄, C₂, and R₅ set up the amount of time the leading edge of the current-sense signal is suppressed from the PWM comparator.

Selecting the components for the leading-edge blanking circuit is simple. You select Q₂ with sufficiently low saturation voltage, V_SAT, to suppress the leading edge of the current-sense signal. You select R₄ and R₅ to drive transistor Q₂ into saturation. You then select C₂ to set up the timing for the circuit. To select transistor Q₂, the maximum collector-to-emitter voltage, V_CE, must be less than the gate-drive voltage. The transistor saturation voltage, V_SAT, must be low enough to suppress the voltage spike at the PWM comparator's input. For most applications, you can get away with using a 2N2222 transistor. You must select R₃ to provide some current-limiting protection for transistor Q₂. R₄ must supply sufficient base drive, I_B, current to Q₂. You select R₅ such that its current is 10% of the base-drive current. You choose the value of C₂ to keep transistor Q₂ saturated for two RC time constants. You can use the following equations to calculate the resistor and capacitor sizes:

and

where V_GATE is the maximum gate-drive voltage of the PWM comparator, and T_BLANK is the amount of leading-edge blanking time required.

Another power-supply design has current-sense spikes so large that the module will not regulate. This design requires the implementation of the leading-edge blanking circuit in Figure 2. The design, a 200-kHz flyback converter, requires a leading-edge blanking time, T_BLANK, time of 200 nsec. The leading-edge blanking circuit requires a maximum base current, I_B, of 42 mA. The I_B specifications require R₄ to be 275Ω and R₅ to be 200Ω. To attain the 200-nsec delay, C₂ needs to be approximately 390 pF. Q₂, a 2N2222 current-suppression transistor, requires a current-limiting resistor, R₃, of roughly 1 kΩ. The PWM comparator's input, I_SENSE, has a peak threshold of 1.5V. Figure 4 shows the current-sense signal of the flyback converter before the addition of the suppression circuit. The waveform shows that leading-edge spikes turn off switch Q₁.

After you add the leading-edge blanking circuit to the power module, it clamps the leading-edge voltage spikes and allows the converter to operate correctly. Figure 5 shows the current-sense waveform. Leading-edge noise spikes on the current-sense signal can cause instabilities in peak-current-mode-control power-supply designs. Usually, you can resolve these issues with an RC filter at the input of the peak-current-limit comparator. In some instances, the noise disturbance caused by parasitic capacitance and gate-drive current can cause the PWM comparator to trip falsely. In these instances, the supply requires a leading-edge blanking circuit similar to this one.