Gate-drive method extends supply's input range

Industrial and telecom applications often require a nonisolated, low-voltage supply from a high-voltage input. IC manufacturers have responded to that need with the application of high-voltage processes and offer control ICs that work to 50V and higher. That voltage is sometimes insufficient, and you need further design techniques to extend the input voltage. The buck converter in Figure 1 represents one such technique. In addition to allowing circuit operation over a wide input-voltage range, the technique reduces power dissipation, because the control circuit does not operate directly from V_IN. The circuit uses a linear regulator and a source-switched driver to buffer a control IC from a line whose voltage is as high as 110V. When you apply the input voltage, current flows through resistor R₂ and zener diode D₂, clamping the gate voltage of FET Q₁ to 9.1V. C₂ reaches a voltage of approximately 6V, which is equal to Q₁'s gate voltage minus its typical turn-on threshold of 3V. FET Q₁ now acts as a crude linear regulator and allows the control circuit to become active.

The source-switched driver of Q₂, Q₄, and Q₅ then comes into play to allow the supply to come into regulation. The TL5001's open-collector output switches to a low state to turn on the main power switch, Q₃. With the gate of FET Q₅ also held at 9.1V and the output pin of the TL5001 low, current flows through Q₅'s drain-to-source pins. The amount of drain current that flows is equal to: (9.1V–Q₅'s turn-on threshold–IC₁'s Pin 1 saturation voltage)/R₄. In this example, this current is nominally approximately 12 mA. Because most of this current flows through R₁, the value of R₁ sets the voltage amplitude used for the gate drive of Q₃. With a value of 1 kΩ for R₁, the voltage across it is 12V. Transistors Q₂ and Q₄ form an npn/pnp pair to quickly switch gate-drive current into and out of Q₃. The base-emitter junction of Q₄ conducts when a voltage drop exists across R₁. This conduction quickly pulls down the gate of Q₃ from V_IN to approximately 11.2V (12V–V_BE). Because Q₃ is a p-channel FET, pulling the gate to 11.2V lower than the source turns it on. When current is not flowing in R₁, the base of Q₂ pulls up to V_IN, a voltage that forward-biases its base-emitter junction.

The gate of Q₃ quickly charges to near-V_IN potential, thereby turning off Q₃. This drive circuit is fast, because none of the transistors operates in a saturated mode; therefore, Q₃ can attain 0.5-µsec turn-on time. This speed means that the circuit can achieve reasonably high operating frequencies with the low duty cycles you encounter in a high-voltage input. You can scale this gate-drive circuit for higher or lower input voltages by the proper selection of the drain-source (or collector-emitter) ratings of Q₁, Q₃, Q₄, and Q₅. All must have voltage ratings greater than the input voltage, and all, except for Q₁, should also be able to switch at high speeds. The addition of diode D₁ offers two advantages. It allows the control circuit to operate after start-up from the output voltage, rather than the input voltage. This method is more efficient, inasmuch as the input voltage is relatively high. A bias-power savings of approximately sevenfold is the result. Also, adding D₁ pulls the source pin of Q₁ to approximately 11.2V, thus Q₁ turns off. All bias power to the controller now comes from the output voltage, and Q₁ no longer dissipates power.