Tool improves design timing

Zenasis Technologies has introduced ZenTime, a tool that uses a hybrid-optimization technology to boost design timing. By operating simultaneously at the transistor, gate, and physical levels, hybrid optimization combines the benefits of custom-cell crafting, physical optimization, and placement-accurate timing.

The tool uses placement-accurate timing to identify timing roadblocks, transistor-level optimization to break the roadblocks by crafting context-specific cells for the critical logic, and physical optimization to restructure surrounding logic. Using transistor-level optimization, ZenTime helps you improve timing using fewer or smaller transistors and fewer intercell wires. The technique improves timing without introducing power, area, or signal-integrity penalties.

Using the tool requires no change to your synthesis or physical-design tools. The crafted cells that it inserts use the same cell-layout architecture as the standard cell library, so placement-and-routing tools see no difference between the standard cells and the newly crafted cells. ZenTime costs $195,000 per year.

Zenasis Technologies, 1-866-936-2747, www.zenasis.com.