Platform supports assertions

Aldec's new unified, assertion-based Riviera-IPT hardware-acceleration platform enhances debugging capabilities and accelerates verification by supporting assertions in both a software and a hardware environment. Using assertions with a traditional testbench usually produces faster verification results and improves the overall coverage with less effort. You can include assertions in the testbench or embed them directly in the design during coding with Riviera-IPT.

In addition to handling assertions in software, Riviera-IPT can compile assertions, along with selected design sections, into hardware. The assertion compiler in Riviera-IPT can produce module checkers in the form of RTL code that you add to the synthesizable portion of the design. Riviera-IPT can then use these assertion checks both at the behavioral, or dynamic, level in the software simulator and at the structural, or static, level in the hardware accelerator. The hardware-based assertion monitors comprise a logical sequence of signals for users to observe and the desired response when the product detects an assertion violation. Once you implement and verify the assertions, they can remain as parts of the final design, and you can use real-time protocol checkers to detect violations during normal device operation.

Riviera-IPT's common kernel architecture supports VHDL, Verilog, SystemC, assertions, and acceleration. It also handles memories, DSPs, and ASICs for joint verification of legacy designs, EDIF-based intellectual-property cores, hardware, and HDL blocks. After you place the verified module in the Riviera-IPT hardware board, it remains "connected" to the remainder of the design residing in the software simulator. Ultimately, most of the design blocks, including assertions, reside in hardware, and the behavioral testbench and SystemC components remain in software.

Riviera-IPT includes an IEEE VHDL, Verilog, and EDIF common-kernel simulator; the Design Verification Manager; a hardware-accelerator board that can handle as many as 12 million FPGA gates; and an interface to a SystemC compiler. The Riviera-IPT system runs on Unix; Linux; and Windows NT, 2000, and XP operating systems. Prices start at $128,000 for a single license, or you can lease the product for less then $22,000 per quarter.

Aldec Inc, 1-702-990-4400, www.aldec.com.