News and New Products

Conference presentation pumps up multimedia muscle

By Brian Dipert -- EDN, 11/13/2003

NeoMagic's MiMagic 6 (Picture), which the company unveiled at this year’s Embedded Systems Conference, is simultaneously an evolutionary follow-on to the earlier generation MiMagic 5 and a revolutionary retargeting of the company’s technology approach to image processing (see “Power-stingy peripheral chips provide partitioning options,” EDN, Nov 28, 2002, pg 14). Focusing first on the evolution piece of the story, you’ll find that NeoMagic migrated from a 220-MHz ARM922T core to a 200-MHz ARM926EJ, in the process adding Jazelle Java-byte-code acceleration, Thumb-instruction-set support, and a 16×32-bit hardware multiplier, along with doubling the sizes of on-chip data and instruction caches. Instead of its predecessor’s CCIR-601 video input, this time around you’ll find an interface that also supports direct connection to an image sensor; because NeoMagic intends that MiMagic 6 can by itself handle all necessary image processing functions. In conjunction with this enhanced capability, NeoMagic expanded the on-chip frame-buffer size to 1.7 Mbits.

How did NeoMagic boost the MiMagic family’s imaging capabilities and still remain within a battery-friendly power-consumption envelope? For the answer to that question, turn to the revolutionary part of the tale. Instead of MiMagic 5’s narrowly focused overlay and color-space-conversion circuits, NeoMagic this time employed a more generic and flexible 160×512-element APA (adaptive-processing-array) matrix, a parallel-processing alternative to conventional sequential-DSP architectures. The approach is particularly appealing in multiple-simultaneous-pixel applications and conceptually also finds use in products from companies such as Atsana Semiconductor and ChipWrights, as well as in FPGAs. The differences between the various companies’ implementations of the matrix-processing concept focus on two primary measures of delineation: the amount of functional integration within each processing cell, and the size and proximity of corresponding storage cell or cells. In MiMagic 6’s very-fine-grained approach, each matrix element contains a primitive logical cell that can execute compare and shift operations—harking back to bit-slice processors of the distant past—along with a 1-bit memory cell.

Although the APA may, as NeoMagic claims, be able to perform 1 billion operations/sec, each one of those operations is rudimentary, complicating performance and power-consumption comparisons with more traditional alternatives. Programming the APA will also be challenging, especially if your legacy code targets a conventional DSP; you’ll probably want to rely on just NeoMagic-supplied libraries. The company hopes to begin shipping product samples by the end of the third quarter; chip-level power-consumption specifications will then be available, and production is slated for the first quarter of next year at less than $18 (10,000). NeoMagic is and has for some time been developing algorithms on an FPGA-based variant of the ARM9 core and peripherals, alongside an ASIC-housed APA. Planned capabilities include MPEG-4 simple-profile and H.263 video encoding and decoding; image-processing operations, such as digital zoom; contrast and color enhancement; auto-white balance and –exposure; and Khronos Group-tailored 3-D graphics-API functions.

NeoMagic, 1-408-988-7020, www.neomagic.com.