News and New Products

DSP core makes magic with complex arithmetic

By Robert Cravotta -- EDN, 8/21/2003

Atmel’s Magic VLIW (very-long-instruction-word) DSP core executes single-cycle complex arithmetic operations that support executing the differential equations and adaptive beam-forming algorithms for hands-free audio conferencing, spectrum analysis, and audio encoding and decoding. The architecture executes 15 operations per cycle and can perform 1 Gflops with 40-bit precision at 100 MHz and at less than
500 mW.

The 128-bit instruction word architecture supports simultaneous execution of both real and imaginary operations and includes 10 floating- and fixed-point operators that are arranged in two identical parallel blocks. The architecture organizes data memory as two banks of 256 40-bit registers with a dedicated datapath that allows them to act as a single bank of 256 complex registers for both real and imaginary arithmetic. The 8-kbyte, 128-bit VLIW on-chip program memory benefits from Atmel’s patent-pending code-compression scheme that claims to improve code density by as much as a 300% without loss of performance.

The Magic DSP core is available now for SOC (system-on-chip) implementation and can support immediate integration with ARM7, ARM9, and Atmel’s 8-bit AVR core. Dual-core SOC implementations can use an ASB (Advanced System Bus) slave wrapper to interface the two cores together and allow the ARM core to access the DSP-memory resources. The SOC prototyping and emulation platform board includes memory subsystems, high-speed SRAM, flash, peripherals, and a Virtex 6000 FPGA for custom IP (intellectual-property) blocks and interfaces with magic and Atmel processors via processor mezzanine boards.

Atmel, 1-408-441-0311, www.atmel.com.