News and New Products

Software tool makes short work of polyglot IP in SOC ICs

By Dan Strassberg -- EDN, 8/21/2003

EEs who design testability features into SOC (system-on-chip) ICs and those who design verification and production-test programs for such devices have to regard Agilent's SmarTest PG (program generator) CTL (core-test language) Browser as a work in progress. Nevertheless, even without the ability to provide waveform displays of test patterns and expected and actual device responses, the software tool can be a huge help to designers of ICs that integrate multiple IP (intellectual-property) cores. Such chips often use cores from several IP vendors and, to develop the cores, different IP vendors commonly use different tool sets. This situation forces SOC designers to simultaneously work with as many as a dozen software tools. Although at least a year may pass before waveform displays appear in Agilent's package, for which a perpetual license costs $72,358 and a one-year license costs $25,168, the current version, which can interpret and simultaneously display data in multiple formats, can simplify and speed SOC design.

Besides supporting the IEEE P1450.6 CTL proposed standard, the browser reads IEEE 1450-1999 STIL (standard test-interface-language) files. STIL is as much as 100 times as efficient in file compression as are other ATPG (automatic test-pattern generator) formats, suiting it well to transmission of files over the Internet. The browser also supports .wgl (waveform-generation-language), .vcd (Verilog-change-dump), and other formats.

Agilent Technologies, 1-800-452-4844, www.agilent.com.