FROM EDN EUROPE: Tiny packages push physical limits

From aerosols with green propellants to that bottle of zinc mineral-supplement tablets with a child-resistant seal, the science that packages everyday consumables typically passes unnoticed. Unnoticed, that is, until the packaging starts to take over. How often have you struggled with some weapons-grade wrapper that flawlessly consigns a valuable percentage of its contents to the floor? With many components now indistinguishable to the naked eye from coffee grains, the electronics industry similarly sees a huge variety of packages that deliver and preserve a vast range of components in prime condition. Until now, the drive to package active and passive components alike has always been toward ever-greater miniaturisation. As a result, we have consumer durables such as clamshell phones with components no thicker than 1 mm. Component-packaging engineers take credit for such products' feasibility.

Of course, such feats arrive at a cost, and there are signs that we're approaching size limits that human dexterity and volume-manufacturing processes impose. For example, just how do you manufacture—let alone prototype—with a 0201 surface-mount resistor that you can scarcely see? Not so long ago, you'd prototype circuits by hand-soldering or wire-wrapping through-hole components. Today's surface-mount technology almost invariably requires you to go straight to a pc board, although there's still an opportunity to breadboard common-outline components using devices such as dual-inline-to-SOIC adapters. Suppliers such as 3M, Amp, Aries, Augat, Harwin, Wells-CTI, and Winslow Adaptics offer ranges of sockets that adapt packages including BGAs (ball-grid arrays), LCCs (leadless chip carriers), PLCCs (plastic leaded chip carriers), and PQFPs (plastic quad flatpacks) for through-hole environments. Test engineers love these adapters, and today's applications for them most often address device-programming and temperature-cycling tasks.

Before you dismiss through-hole assembly as an anachronism, remember that this technology continues to serve many mass-market consumer needs. Significantly, the continuing availability of easy connectivity ideally suits the education market. Such easy connectivity also suits the semiconductor manufacturers, which frequently use ceramic DIP (dual-inline-plastic) packages to house prototype silicon. And, for both local manufacturers and those in developing countries, through-hole technology suits the array of automation machinery that pervades the secondhand-equipment market. It's telling that DIP packages appear as alternatives to surface-mount devices for Motorola's recent Nitron microcontroller family, which targets high-volume, lowest cost applications. Development support includes a $25 evaluation board that uses an eight-pin DIP version to ease access to its pins. Functionally, this 55×65-mm, single-sided, through-hole board replaces multiple boards in the vendor's original M6800 development crate—in the meantime furnishing far more features and better performance at almost infinitely lower cost. But the prize for today's smallest general-purpose microcontroller goes to Cygnal's 8051-based mixed-signal family. Selling for approximately €2 (10,000), the company's C8-51F300 packs an 8-bit ADC with 8 kbytes of flash memory into a leadless package that measures just 3×3 mm.

Within normal component-size limits, the complexity that typifies most designs relegates prototyping considerations to the bottom of the pile. Until you need to swap a device, you're far more likely to concern yourself with higher profile issues. But resist the temptation to use the smallest available parts in proof-of-concept designs. If you know that you're going to need select-on-test values, use parts with dimensions that you can easily swap out. And it's worth understanding what you can achieve in-house without going to expensive pick-and-place test runs. Hand soldering is still feasible for many surface-mount packages and often the only option when you need to rework an assembly. It's even possible to rework BGAs by hand. However, this task is typically left for specialist subcontractors, such as Circuit Consultants. Before you even get to a prototype, pc-board designers may ask why they still have to draw each new package variant by hand. For an industry that freely provides complex device-simulation models for downloading, surely it can't be impossible for vendors to provide recommended land patterns in a standard electronic format?

Power MOSFETs are one of the most prolific areas for packaging innovation, with developments such as Fairchild's bottomless SO-8 and Vishay's PowerPakSO-8-compatible outline, which replace and outperform chunky TO-252/263 parts. But the most radical package to date is International Rectifier's leadless DirectFET. (See Reference 1 for the full MOSFET story.) Mark Pavier, research manager at the company's packaging facility at Oxted, UK, points to the thermal- performance improvement that DirectFET gains by abandoning plastic over-moulding: "Using a copper can rather than mould compound slashes thermal impedance and enables double-sided cooling, effectively doubling power density per unit area." Pavier is also keen to highlight other achievements, such as housing the IRF6156, a 20V bidirectional MOSFET that targets protection circuits for lithium-ion battery packs. By similarly dispensing with lead-frame and moulding compound, the FlipFET solder-bump wafer-level package occupies about 20% of the area of an equivalent TSSOP. Measuring just 0.8 mm high, the device also lowers thermal resistance from around 60 to 35°C/W. Because energy density is crucial for cell-phone battery-packs, using the FlipFET package reduces the protection-circuit volume and maximises the space that's available for energy storage. Pavier also highly regards other options, such as the iPowir multichip-module series of synchronous buck-converter circuits, which target single and polyphase dc/dc converters. Using this technology optimises the analogue-driver-to-FET interface, enabling a device such as the iP2002 to continuously output 30A from a power-BGA package that measures 11×11×2.6 mm (Figure 1).

Because you still have to remove the heat from the pc board, you're unlikely to push the maximum current ratings of small-outline power MOSFETs. Rather, you're likely to take advantage of their low conduction losses to constrain heat generation. Jos van Loo, business-development manager for power-management products at Zetex, acknowledges that, although solderable pads improve heat transfer into the pc board, you must consider the copper area that's necessary to dissipate conduction losses. This consideration, says van Loo, is a principal limitation in package-size reduction: "There's little point in shrinking packages further if there's no improvement in thermal efficiency." Van Loo believes that the migration from SOT-23 (small-outline-transistor-23) to MLP (moulded-leadless-package) devices provides engineers with the performance they need today and for the next few years, without overchallenging manufacturing processes. He considers that MLPs comfortably accommodate existing SOT-23 applications operating at as much as 3A that dissipate 200 to 300 mW and whose dies fit within a 1-mm-high moulding.

MLPs suit low-power Schottky diodes that previously demanded bulky SMA-outline packages with height dimensions approaching 3 mm. Zetex has just introduced its ZXSDS2M832, a dual 1A/60V Schottky diode in an eight-lead MLP that—like many other Zetex devices—is optionally available in lead-free packages. Van Loo reports that, although European legislation mandates that all designs be lead-free by June 1, 2006, Japan is driving today's lead-free market. Although Japanese multinationals consider that lead-free consumer products add prestige, semiconductor vendors and OEMs closer to home struggle to convert their product lines to lead-free equivalents. Qualification issues are also difficult and expensive for both parties. Although current demand for lead-free devices is only around 5%, van Loo perceives lead-free products as a major opportunity for his company: "Next year's demand is very uncertain, but vendors with a track record of supplying lead-free devices will inevitably attract customers."

Motor-drive applications especially benefit from the design simplification that integration brings. Here too, the trend toward smaller parts with high power densities meets physical limits. Allegro Microsystems' A3977xLP is a 100W-rated stepper-motor driver that comes in a 28-pin, 10×6.5-mm TSSOP that features a solderable pad beneath the package. A forthcoming H-bridge driver packs a similar rating into a 16-pin TSSOP that measures just 6×5 mm. Bob Christie, Allegro's European applications manager, explains that although these parts are rated at about 3A and 35V, the main limitation is power dissipation: To minimise dissipation, he notes, Allegro chops the output so that the output transistors are always passing load current at their lowest on-resistance. The motor's inductance then averages current flow. Because power dissipation relates only to the output transistors' on-resistance and the load current, it's possible to drive higher power loads, such as 42V automotive motors, using the same small package. But beyond about 3A continuously, on-resistance pushes dissipation beyond package limits to demand external FETs.

Be sure to qualify the mounting methods and the copper area that vendors use to specify thermal performances. Allegro uses the JEDEC-standard high-effective thermal-conductivity test board (or "hi-K board") as one vehicle for characterising heat dissipation. The hi-K board uses conventional, 1.6-mm-thick FR4 construction with two outer layers of 70-micron copper and two 35-micron inner layers. To optimise heat transfer from the IC's solderable pad into the pc board, a 3×5 array of 0.3-mm thermal vias on 1.2-mm centres passes through the board. These thermal vias connect the top, second, and bottom layers, leaving the third layer unconnected. The top signal layer carries the IC's solder connections and fan-out tracking; the second and third layers are solid, representing typical ground and power planes; and the bottom signal layer carries the via solder-lands. As a result, the junction-to-ambient thermal resistance can be as low as 28°C/W, allowing this 28-pin TSSOP to dissipate more than 3W at room temperature.

Tools that can help you analyse power-dissipation performance include thermal-modelling simulation software and infrared-imaging cameras that reveal the heat profile across an assembly. Thermal modelling for Allegro's test board shows that, even for 25% solder coverage of the exposed pad, the thermal vias constrain temperature rises to about 6% compared with 100% solder penetration (Picture). Allegro's Christie notes that, in many designs, the ground plane on the back of the board provides thermal contact to a heat sink, reducing the junction-to-ambient resistance to as little as 20°C/W; in extreme cases, mounting the thermal pad directly to a heat sink can yield roughly 5°C/W. According to Christie, the prototype circuit must usually use all the board-layout techniques that the final circuit requires. Automotive applications are especially demanding; the operational environment demands components that withstand –40 to +125°C or more. Christie remarks that "under-the-hood" temperatures are typically 105°C, but they can reach 125°C around headlamps or exceed 135°C when you mount a module directly on the engine or in the gearbox. "With maximum junction temperature for silicon ICs usually quoted as 150°C," notes Christie, "there's not much room for high dissipation or high thermal resistances."

Cynthia Trigas, technology manager at Motorola's advanced-interconnection-systems laboratory in Munich, typically focuses her attention on packaging options for automotive semiconductors. Most often, her customers' enthusiasm for system-in-package devices demands various control and power-delivery elements within a single, easy-to-use component. Although many propositions are available, according to Trigas, Motorola has to decide what it can standardise "to enable high-volume competitive pricing for these new devices." Trigas describes a packaging-design process that reduces to three main areas: functional partitioning, electrical and mechanical behaviour, and what Trigas refers to as "software issues." Where power is concerned, Trigas says that 25A peak switching current currently bounds the cost-effective region in which you may choose to partition power and control circuitry. But to determine how best to divide the circuitry into multiple dies and optimise the package design, designers must first understand the whole system (see sidebar "Multiple dies maximise density"). Software difficulties can arise here, because the die libraries from disciplines such as power, embedded-control, and memory groups may use different library constructions that complicate the analysis of the interface characteristics. These formats must harmonise to allow engineers to analyse the most effective partitioning concept; part of this analysis involves determining parameters, such as worst-case junction temperatures and overall package heat dissipation. Thermal-simulation tools that derive compact thermal models from die-library information and package construction permit engineers to evaluate signals that represent the end user's application (Reference 2).

In parallel with considering internal construction, Trigas considers how users will mount and interconnect the component. Trigas asserts that Motorola tries "to work on a platform concept and ensure that the parts will function effectively" after you mount them to the pc board. Other challenges that packaging engineers increasingly face include "green-environment" material changes, such as lead-free solders and halogen-free moulding compounds. Because lead-free solders require elevated reflow temperatures, and new moulding compounds require extended evaluation for moisture resistance and mechanical integrity, such new materials demand even more reliability assessments than do their predecessors. Routine tests include accelerated life testing, such as temperature shock, in which devices under test experience a series of rapid and extreme temperature changes until they fail. According to Trigas, Motorola aims not only to determine that the part will pass the required reliability test conditions, but also to continue testing until the part fails. Trigas emphasises the importance of determining how the part failed and the implications that these failures may have on normal use. As another part of the package-development process, Trigas must also consider natural variations in manufacturing processes over a product's lifetime, such as the wear to tooling after making millions of devices. She recognises that "establishing where variations are likely to occur" is all part of developing a robust process to ensure that Motorola supplies its customers with a reliable product.

Ken Murphy, Fairchild's marketing manager for new logic products, observes that today's multirail system-on-chip products create new demand for glue-logic and interface ICs. Although SOICs (small-outline ICs) still account for the bulk of the discrete-logic market, applications such as cell phones often require a single-gate function. Worth some e3 billion annually, the single-gate "bit business" has evolved beyond simple logic gates to embrace functions such as decoders, flip-flops, and the analogue switches you need to route audio and video signals. There's also a trend toward wider gates that previously required multiple single-gate devices. Chip-scale LGA (land-grid-array) packages, such as Fairchild's MicroPak, accommodate the six to eight terminals that multiple-input gates require in a footprint as small as 1×1.5 mm and save around 82% of pc-board space relative to an SOT-23 device. Including its leads, a conventional three- to six-terminal, SOT-23 outline is relatively massive at 2.9×2.85 mm and—crucially for third-generation cell phones—MicroPak shrinks the height dimension to 0.55 mm, down from an SOT-23's 1.2 mm.

Murphy acknowledges that miniaturisation is useless if his customers face serious manufacturing challenges, noting that he'd be "frightened to bring out new products without partnering with a real end user." Despite its diminutive size, MicroPak has terminals and a 0.2×0.3-mm pc-board land-pattern that maximise the board-attachment area (Figure 2). The terminal pitch is 0.5 mm, which Murphy sees as today's optimum geometry. In common with other leadless package styles, MicroPak alleviates skewed-pin and coplanarity problems. Compared with a flip-chip, bumped-die package of similar dimensions, show that MicroPak is more rugged in the drop-and-shear tests that simulate real-use damage to portable products, according to tests by a cell-phone manufacturer. Unlike LGA designs, such as MicroPak, flip-chips have a history of requiring an underfill to increase pc-board-adhesion strength. Data also demonstrates that MicroPak's adhesion qualities exceed those of a comparable flip-chip by more than 62% in extreme-temperature-cycling tests.

Murphy also points to the leadless QFN (quad-flatpack no-leads) package styles that shrink conventional glue-logic and level-translation functions by as much as 65% over TSSOPs. Vendors already consider QFN as a new packaging standard, and available variants include Fairchild's DQFN (depopulated quad-flatpack no-leads), Philips' HVQFN (plastic, thermally enhanced, very thin quad-flatpack no-leads), and the QFN from Texas Instruments. These leadless packages don't require filleted terminals that extend the height of the component to guarantee adhesion strength, such as you see in resistor arrays from Phycomp's popular ARC and ARV ranges. In the case of the QFNs, the size of the package's lands and the pc-board land pattern are sufficient to control the surface-tension forces that settle the package during the solder-reflow process. But, like the resistor arrays, QFN terminals appear at the package's periphery to permit visual-examination procedures, such as AOI (automated optical inspection) during manufacture. Conversely, BGA package styles require x-ray inspection that adds another process step and thus increases manufacturing costs.

Along with Integrated Device Technology and Renesas, Texas Instruments recently announced QFN-package options for a broad line of logic families. Available in 14-, 16-, and 20-terminal packages, these families encompass virtually all standard gate and octal functions. Retaining the same pinout as an equivalent TSSOP device, a pad beneath the device improves thermal performance by as much as 55%. The devices also offer a substantial decrease in parasitics with reductions in capacitance and inductance of 30 and 60%, respectively, compared with TSSOPs. The tin terminal material suits lead-free SnAgCu (tin-silver-copper) or conventional SnPb (tin-lead) eutectic solder pastes. Mario Bolanos, semiconductor-group packaging-technology-development director at Texas Instruments, also points to his company's NanoStar products, which represent the only wafer-scale five-, six, and eight-pin logic devices available to date. The five- and six-pin devices measure just 1.4×0.9×0.5 mm; at 1.9 mm, the eight-pin variant measures 0.5 mm longer. Connection to the pc board is through SnPb or lead-free solder balls that are available in 0.17- and 0.23-mm-diameter options. The smaller diameter ball suits a 0.175-mm land with a 0.35-mm conventional NSMD (non-solder-mask-defined) aperture. The larger ball stretches these dimensions by 0.5 mm, but in each case, the ball pitch is 0.5 mm.

With a product portfolio that ranges from single-gate devices to what is fleetingly the fastest DSP available—the 720-MHz TMS320C6416—Bolanos' group is never short of challenges.) A 1-GHz version is coming soon.) Key considerations for DSPs include optimising the pinout to optimise the ground-pin arrangement to minimise I/O switching noise without complicating connectivity issues for pc-board designers. It's also important to reduce cost as much as possible, because DSPs can be more price-sensitive than, say, ASICs. Other notable packaging challenges include the company's OMAP (open-multimedia application-platform) project, which aims to deliver cost-effective chip-scale devices, primarily to third-generation-handset manufacturers. It's essential for semiconductor vendors to work closely with such key-account customers to smoothly bring devices that can carry 300 I/Os on a 12-mm-sq body into volume manufacture. Interestingly, until as recently as a couple of years ago, semiconductor-device designers typically worked independently of their packaging engineers, but this is no longer the case at any leading vendors' facility. Bolanos and his contemporaries agree that today's interdependencies between the silicon and its package are crucial: "We have an integrated chip-package-co-design philosophy, but, even so, it's very difficult to get everything right the first time."

If today's packages push manufacturing technology, what's in store over the next few years? Recognising PC voltage-regulator modules as power-market technology drivers, International Rectifier's Pavier sees the trend toward increasing power density and lower parasitics continuing. "We'll have greater integration where it's truly beneficial," he says.

For physical formats, Fairchild's Murphy believes that it will take two to three years for manufacturing processes to catch up: "Smaller packages and terminal pitches aren't likely anytime soon—or at least, until 0.3-mm-pitch devices become easy to assemble."

Looking further down the road at Texas Instruments, Bolanos foresees top-end flip-chip products with a die size greater than 20×20 mm that will need more than 10,000 I/Os. "Underfill will be a major challenge, along with thermal and current-density concerns," he says. Midlevel products, such as ASICs, will exhibit similar concerns of lesser degree, but signal integrity is likely to be a major concern. Overall, he says, the capabilities that your automation infrastructure provides will continue to dominate manufacturability issues.

Meanwhile, for an example of contemporary packaging achievements, see RockyLogic's Ant16 logic analyser (Figure 3). One key to its $399 price tag is that this 16-channel device occupies a standard plastic case that typically houses USB-to-RS-232 converters. The USB connection provides power to the Xilinx FPGA via an SOT-23-packaged LTC3406 switcher from Linear Technology that requires one inductor and two capacitors to transform 5V dc to the FPGA's 1.8V levels. A DAC sets the FPGA's threshold levels to suit the user's logic family. The USB interface is a single chip from FTDI, which the Ant's designer, Tim Eccles, chose because it comes with drivers "for every operating system you can think of, ready to use." The heart of the device is the FPGA and its embedded SRAM, which Eccles operates in banks to downconvert the 500-MHz maximum sample rate across 16 channels to 125 MHz×64 bits. Together with semiconductor technology, Eccles acknowledges, low-cost packaging components make the project feasible. "If the enclosure hadn't been able to accommodate the 20-pin header you need for 16 channels, a clock, triggers, and ground, it would have been 'game over,'" he says.