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Is Moore's Law Irrelevant?

By Ed Sperling -- Electronic News, 8/14/2003

After 38 years of defying the naysayers, Moore’s Law remains as viable as ever from a technology standpoint. There’s only one problem -- fewer and fewer companies are following it.

The push to smaller process geometries, copper interconnects and low-k materials has set the stage for some of the most significant changes in the history of the electronics industry. Interviews with dozens of executives from around the electronics industry point to the following:

·    At 90 nanometers and below, the concept of mixed signal integration has hit a wall. While companies are still making tradeoffs, two of the biggest players in this space -- Analog Devices Inc. and National Semiconductor Corp. -- are changing direction in favor of multiple chips in a single package or in multiple different packages.

·    Power leakage has become such a headache at 90nm and below that the concept of “on” and “off” has become a relative term. Most companies say that even with multiple power domains and prioritizing which functions remain on all the time and which ones can be powered down, multiple older-generation chips may be preferable -- particularly when they’re combined in a new package.

·    Design costs and delays are emerging as the biggest hurdle in creating new chips, replacing production costs and yield issues as the biggest concerns for chip companies. Fully utilizing 100 million gates at 90nm could take, according to one estimate, as much as three years, while time to market is shrinking to as little as six months.

What has changed is that economics are now taking precedence over technology decisions, say executives from all sides of the industry. And while most believe that from a technology standpoint every issue can be solved -- even though there may be some pain in getting there -- they say that way of thinking may no longer be relevant.

“The world is being split between the have nots and the haves,” said Dennis Monticelli, national fellow at National Semiconductor. “There are two basic problems at 90 nanometers. One is that portable devices drain power. The second is that heat builds up and you cannot properly extract it. Those two issues have to be solved or there will be a train wreck. The interesting thing is that there is not one set path. The solution hasn’t been found.”

Monticelli said there are a slew of new circuit tricks being developed on the circuit side that help the issue. But he said that with SOC designs -- particularly those involving both analog and digital -- it becomes more difficult to merge the two worlds at smaller and smaller geometries.

“There was a trend to integrate everything on a chip,” he added. “We’ve come to the conclusion that it’s not worth it for the majority of applications. You will see a divergence in the future. The customer will continue to want a one-package solution, but that probably won’t be a single chip…There is not a technology problem we can’t solve. But being able to do that and being able to do that economically are two different things.”

Dave Robertson, product line director for Analog Devices’ high speed converter communications group, said that mixed signal got a free ride in the 1990s. He said it all worked out fine until chip sizes hit 0.5-micron. But at 0.25-micron, voltages dropped to 2.5 volts, which pushed the analog’s signal-to-noise ratio through the floorboards.

“For the digital guys, this was no big deal,” Robertson said. “And for modest performance circuits, it was no problem to go to 3 volts. But as you move to less than 2 volts and less than 1 volt, it gets pretty difficult.”

Robertson said that for things like cellular communications, there are still three to six chips instead of one. And he said that trend would continue in many other applications as chip geometries shrink. “The solution is that you don’t just keep porting the same design onto new technology. You need a new architecture and a new topology.”

In many respects, you also need a new way of looking at the problem. Even Gordon Moore has his doubts about the future of the law that bears his name. Late last year he presented a paper that said 45nm would be the end of the road.

“The end of Moore’s Law is not going to happen when an insulator doesn’t insulate,” said T.J. Rodgers, president and CEO of Cypress Semiconductor Corp. “It will happen when the next wafer becomes a science project, not a product.”

Rodgers compares it to riding a train out of New York’s Grand Central Station. He said the first stop costs $2 and the second stop costs $4, and the price gets more expensive each stop. “We’re now in Connecticut at the $128 stop and people have been getting off at every stop in between -- 130nm was the last cheap development node.”

The sheer complexity and time it takes to design new chips at 130nm and below is growing exponentially. For applications such as memory chips, there is sufficient volume to justify the design costs. But the number of applications that can be assured of that kind of volume is shrinking as chips become increasingly specialized.

Kevin Meyer, VP of worldwide marketing and foundry services at Chartered Semiconductor Manufacturing, said that moving from 0.13-micron chips on 8-inch wafers to 90nm on 12-inch wafers provides five times the number of dies for 1.8 times the cost. And with yield issues largely being handled by the foundries that is no longer an issue. But designing the chips has turned into a nightmare.

“Design is what’s changed,” Meyer said. “A device at 90nm is a full SOC. OEMs who are buying the chips are also saying you have to supply the real-time operating system, drivers, key applications, and you have to put it on a development board. The whole chip has to be on a development board. That is a much bigger challenge.”

Meyer said that getting to market faster by integrating all of the pieces onto smaller chips is playing heavily into the hands of established IDMs such as Intel Corp. and IBM Corp. rather than the whole fabless model. He said the industry will likely split at that point into fabless assemblies of intellectual property and components and chips from the IDMs.

Cypress’s Rodgers agreed, saying the industry has split at 90nm and that this schism is not going away.

“The whole fabless model is a bug headed for the windshield of a car,” he said. “Small companies don’t have the sophistication to do state-of-the-art design. The cost used to be a bunch of guys who got together in a garage and built a $5 million chip. And if they could sell it for six times that amount, it was a good business proposition. Now you need a much larger team of designers and it costs $20 million to $40 million for the first chip.”