News and New Products

Tool eases sizing, verifying

By Gabe Moretti -- EDN, 9/25/2003

Neolinear has released Version 2.2 of its NeoCircuit product that aids designers in sizing and verifying custom analog-RF and digital-circuit topologies. Engineer can use the tool in conjunction within their analog-simulation environments. Neolinear has enhanced the sizing algorithm and improved the integration with both Nassda (www.nassda.com) HSIM and Cadence (www.cadence.com) UltraSim simulators to improve block-level sizing and verification. Designers often must modify transistor sizes and device spacing to account for local and global mismatching to optimize yield and circuit manufacturability. The new version of NeoCircuit includes sensitivity and correlation analysis of Cadence’s Artist-generated Monte Carlo results, including scatter plots. Using the tool, designers can determine and account for mismatch effects.

In addition, the tool includes multivariable, multigoal local optimization algorithms that designers can use to find enhanced circuit alternatives. Correlation matrices and parallel coordinates allow engineers to size circuits and visually inspect and analyze them. Neolinear has enhanced the integration with Agilent (www.agilent.com) ADS simulator and the Cadence Analog Design Environment to include RFDE (RF Design Environment) integration. The integration with NeoCell now provides users of the tool with an ECO (engineering-change order) capability. NeoCell tightly integrates with the Cadence custom-design flow and many commercial parameter-extraction products. The result of both integrations is that engineers can now resize devices and adjust layouts and minimize the number and length of design iterations. The list price for NeoCircuit for a one-year, time-based license is $85,000.

Neolinear, 1-412-968-5780, www.neolinear.com.