Accumulating enough samples to effectively and accurately measure linearity errors in pipeline converters at production test and minimizing test time are difficult enough. Add to that multiple sites, multiple channels, and the expense of multiple custom-instrument resources during periods of low capital expenditure, and engineers must think creatively to increase throughput without sacrificing yield. Many test approaches are beginning to rely more on FPGAs. These ICs' high speeds and flexible usage lend them well to ATE (automated-test-equipment) shortfall workarounds and pare down final test time, which could add up to thousands of dollars in savings, depending on time saved and volume. But development of FPGA designs can be time-consuming and expensive; outsourced designs can cost more than $100,000, depending on complexity. Also, the hardware-histogram capability of many ATE systems is expensive, and you must multiplex it to multiple sites, which reduces its time-saving effectiveness. This Design Idea presents a simple, discrete hardware-histogram circuit module (Figure 1), which uses off-the-shelf components, requires no software, is easy to debug, and is easy to multiply to many sites and channels.

The circuit of Figure 1 shows how you can configure a FIFO memory, a static SRAM, and a bus register to generate fast hardware histograms for linearity tests and still allow straight data acquisition for other tests. The main purpose of the FIFO memory is to collect data at the speed of the DUT (device under test), because, with all the data-swapping that occurs during the histogram routine, the cycle is slower than the DUT. But it also reduces switching noise in the test circuit by keeping the outputs and the other devices "quiet" during the initial acquisition. And, because many high-speed converters require low-jitter sources, the use of the FIFO memory eliminates the need to synchronize the test head with external sources by using the system clock to run the rest of the circuit.

The SRAM stores each bin count in the address whose value is equal to the code being accumulated. The memory is generally underused, because part of the memory holds a look-up table of all practical bin counts. Rather than use an adder or a counter to implement the bin-count function, which would require an extra IC, this circuit implements data+1 by storing each look-up entry in the address whose value is one less than the value stored at that location, not including bit 16. Address-bit 16 keeps the bin counts and look-up table in different columns. When each sample routes from the FIFO memory to the address bits, the FIFO memory's output becomes disabled as the bin count for that code appears on the bus. The bus register's "bus-hold" function conveniently holds the current bin count on the address lines while the SRAM's address-bit 16 is toggled to access the count look-up table, and the bin count+1 appears on the bus. The bus register latches in the new bin count while the FIFO memory reasserts the sample data.

The SRAM then accesses the bin count (address-bit 16 reset) in write mode when the bus register reasserts the new bin count with the FIFO memory disabled. This cycle plays out until the histogram is complete and the data is read through the bus register to the test head. Figure 2 shows the timing scheme. Although the FIFO memory has a depth of only 64 kbytes, note that the FIFO memory can be filled multiple times and the histogram can be updated multiple times until the SRAM is cleared. You encounter no overflow, regardless of bus width, as long as no bin count exceeds 16,383. The look-up table can be written before any device is tested, and the bin counts can be reset between tests when the handler is binning. This circuit is particularly useful when your application requires multiple sites or multiple channels, because you can simply plug the inexpensive module into other sites or channels and operate it in parallel.