News and New Products

Upgrade backplanes to 10 Gbps with 0% coding overhead

By Nicholas Cravotta -- EDN, 12/11/2003

Transferring payloads as fast as 10 Gbps per differential pair with 0% coding overhead, the AN6420 quad high-speed backplane SERDES (serializer/deserializer) transceiver from Accelerant Networks operates at 6.25 to 10 Gbps using PAM4 (passband-amplitude-modulation) multilevel signaling (Picture). The device also interoperates with SERDES that operate as fast as 5 Gbps with DFE (decision-feedback equalization) in binary mode. You can use DFE to open eyes as small as 5 mV to guarantee signal integrity.

Traditionally, coding schemes, such as 8B/10B or turbo coding, improve the robustness of a link by providing an error-correction mechanism—usually, an embedded pattern—within the raw bandwidth of the link that may enable limited repair of corrupted data, thus increasing the BER (bit-error rate). Additionally, coding guarantees a certain transition density, giving the data enough transitions for the receiver clock to lock onto the signal. Coding thus improves the effective BER of a link; for example, with turbo coding, a link with a BER of 10¹⁰ might increase to 10¹⁸ but at the cost of as much as 25% of the available bandwidth.

The AN6420 adds 0% coding overhead by achieving a BER of 10¹⁸ through other means, eliminating the need for coding and the associated loss of bandwidth. The transmitter includes a random polynomial scrambler, which guarantees transition density and uses a lossless-compression scheme to account for extreme-transition cases without increasing the payload. A distributed-digital-PLL architecture retimes signals traveling from one side of the chip to the other to keep jitter less than 2 psec rms. Additionally, Accelerant's "lab-in-a-chip" technology has undersampling, margining-algorithm, and vector-analyzing diagnostic units to produce an in situ BER to track link reliability on a per-link basis. You can access BER data via registers and analyze it using a company-provided GUI, which Accelerant based on the Mathworks’  (www.mathworks.com) MatLab.

Because the effective overhead is 0%, you can use the entire bandwidth to pass data; in typical 8B/10B encoding, 25% of the bandwidth is encoding overhead. For example, instead of requiring 6.25 Gbps to pass a 5-Gbps XAUI (10-Gbit attachment-unit-interface) data stream, the AN6420 can operate at 5 Gbps. Running at a lower frequency reduces overall power consumption and enhances the range of backplanes over which the device can reliably operate.

In addition to operating as far as 60 in. over FR4, the AN6420 supports both transmitting and receiving equalization, has continuously adaptive seven-tap transmitter equalization, loss-of-signal detection, programmable per-channel BER tester), ±400-ppm frequency offset, and the ability to receive and transmit asynchronously. The device also has a quad 2-to-1 back-plane multiplexer, allowing such functions as the multiplexing of two 3.125-Gbps XAUI channels onto a single 6.25-Gbps channel. The AN6420 consumes 0.2W of power per 10-Gbps channel across 20 in. of FR4 and two backplane connectors.

Currently available for sampling, the AN6420 uses a 0.13-micron process, and the company plans to build a later version on a 90-nm process. It comes in a 17×7-mm, plastic BGA package. It costs $80 per unit (volume quantities).

Accelerant Networks, 1-503-466-9231, www.accelerant.net.