FPGA-configuration scheme is flexible

FPGAs are popular in circuit design because of their flexibility and efficiency. You need to program an FPGA by loading configuration data into designated configuration memory. Because most FPGAs have no internal nonvolatile memory, you must store the configuration files in external devices. When you use many FPGAs in a design, it is inadvisable to put a large amount of external memories near the FPGAs. The memory consumes a lot of area and increases the difficulty of the pc-board layout. Consider Xilinx (www.xilinx.com) FPGAs. Xilinx offers daisy-chaining techniques to program multiple FPGAs from a single source. However, when you want to change only one FPGA's functions and keep others unchanged, it is unwise to reprogram all FPGAs, because it takes a lot of time and can cause unexpected problems in the related circuits. This Design Idea describes how to individually program multiple FPGAs with limited resources. It uses a serial port of the Analog Devices (www.analog.com) ADSP21065L to arbitrarily program four FPGAs (Figure 1).

A DSP processor, the ADSP21065L, serves as a microcontroller to program the FPGAs. The configuration bus consists of the Clk, Data, Program, Init, and Done signals. The output data from the ADSP21065L is synchronous with the Clk signal, and the Program (output), Init (input), Done (input), and two control signals (output) are the ADSP21065L's I/O flags. The rest of the circuit comprises four FPGAs from Xilinx. The arrows to the FPGAs represent the configuration bus. The trick is in the so-called switchboard, which traces the configuration bus to an FPGA according to the ADSP21065L's control signals. At first thought, some bidirectional buffers, for example, 74LVT16245s, would seem suitable for this requirement by linking the control signals to OE and T/R pins of the buffers.

But after taking a closer look at the situation, this approach would be difficult because the Init and Done are output signals from the FPGAs, which you cannot merge together. Therefore, the "buffer" you are looking for should have multiplexing or demultiplexing capabilities. This design uses the 74FST3253 dual 4-to-1 multiplexer/demultiplexer bus switch from On Semiconductor (www.onsemi.com) to implement this function. By connecting two control signals to the two select inputs, S0 and S1, you can cause I/O Signal A to connect to I/O lines B1, B2, B3, or B4, respectively, if the value of the two control signals are 00, 01, 10, or 11.

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