News and New Products

No fable: the FPGA in CPLD’s clothing

By Brian Dipert -- EDN, 5/13/2004

Altera goes to great lengths to promote its Max II family as a CPLD product line. Far more accurate, though, is to say that Max II pursues CPLD business opportunities, because when you look under the hood, you find a fairly traditional LUT (look-up-table)-based FPGA architecture inside.

Granted, Altera has made routing tweaks and other enhancements intended to improve Max II chips’ timing predictability over conventional FPGAs. And, as CPLDs have become more complex, with hierarchical interconnect matrices to cost-effectively increase density, and multiple signal paths within and between macrocells to improve pinout-locking capability, their timing has become more capricious. But, it’s a bit of a stretch to equate Max II with the highly predictable, product-term and global-routing matrix-based CPLD that most of us think of when we see the abbreviation.

Positioning aside, Max II is a compelling alternative to antifuse FPGAs or exotic, expensive CPLDs for those of you whose designs incorporating stage machines, address decoders and other historically CPLD-tailored circuits have grown beyond 128 macrocells in size and who also might want to add FPGA-tailored circuits, such as bus bridges, in the same device.

Based on the flash-memory-inclusive variant of TSMC’s 0.18-micron process, Max II chips embed their configuration memories and are fully functional less than 200 μsec after the application of stable system power. Conceptually, they’re reminiscent of Lattice Semiconductor’s ispXPGAs, although little overlap exists in the two vendors’ families’ logic-density ranges. You can run Max II parts at 1.8 to 3.3V supply voltages; an internal regulator downconverts the externally supplied voltage to 1.8V, and 1.8V-only device variants are also available that bypass and turn off the regulator, thereby reducing standby-power consumption.

Other intriguing Max II features include the ability to in-system reprogram the nonvolatile configuration memory while the logic in the SRAM-based portions of the chip is running; a separate, dual-block, 8-kbit, user-accessible flash-memory partition; and nominal design-compilation time of less than 1 minute, with space-optimized compilations taking no more than 40 minutes. You cannot testdrive Max II silicon until the third quarter, but those of you who received Version 4 of Altera’s Quartus II design software or have downloaded the latest version of the free Quartus II Web Edition can now begin your development work. (Altera also plans to offer AHDL support for Max II.) Table 1 lists key product-family features and 2005 price projections.

Altera, 1-408-544-7000, www.altera.com.