News and New Products

Network search goes low power and small

By Nicholas Cravotta -- EDN, 5/27/2004

HyWire’s new HySem and HyCount algorithmic-network-search technologies target use in low-end and midrange routers and switches. Traditionally, TCAM (ternary-content-addressable-memory)-based search engines have dominated these applications because these applications have low-latency requirements. However, as look-up tables continue to get bigger, especially with the move to Internet Protocol Version 6, power consumption in TCAM-based search engines also increases because each table entry must be active during a look-up. As a result, algorithmic-search engines have begun to look more attractive for applications with more latency tolerance because they consume significantly less power, and use DRAM, which is more cost-effective than are TCAM cells.

The HySem search-engine manager implements forwarding-information-base and classification-information-base functions in routing and switching, offering as many as 400 million searches/sec in the standard SOC (system-on-chip) product and as many as 100 million searches/sec in HyWire's HyFlex FPGA module. The company claims that the engine can provide higher throughput but that today's memory speeds limit the device. The engine outputs a result each clock cycle in forwarding applications and can simultaneously look up eight times as many using the same key. Other features include the capacity to store more than 6 million Internet Protocol Version 4 entries in an SOC, based on available memory; multiple-look-up-table support; deterministic-search latency, use of standard DRAM devices, including RLDRAM I, RLDRAM II, and FCRAM II; and optional integration with HyCount for accounting, billing, and similar functions.

The DRAM-based HyCount coprocessor provides massive-statistics accumulation and key event monitoring of packets crossing routers, switches, or network appliances. Applications include database accounting and billing, flow control, detection of traffic violations, and detection and prevention of harmful traffic. HyCount can collect as many as 200 million counts/sec per counter, supports as many as 2 million counter/timer groups or 4 million counter/timer groups at 100 million counts/sec, and has five programmable-width fields per group. It provides packet- and byte-count aggregation and reporting, time-stamp updating, maximum-event-rate-violation detection and reporting, and time-out-expiration detection and reporting. This device enables carriers to measure the exact traffic for accounting and billing at the backbone and edges of the network, as well as detect denial-of-service attacks and intrusion attempts.

Both the HySem and HyCount will be available as soft macros or standard products. The gate-array version of these cores consumes 3W; a four-RLDRAM (2W each) device will consume a total of 11W with a capacity of 6 million entries and performance of 400 million searches/sec.

HyWire also offers HyFlex, a general-purpose, stand-alone module based on Xilinx's (www.xilinx.com) Spartan III 2000 FPGA. HyWire packages the module as a single device with a 65×65-mm, BGA-compatible FG900 footprint and includes three Micron (www.micron.com) 288-Mbit RLDRAM II devices and 8 Mbits of flash memory. You can load the HySem, HyCount, or other soft macros into the onboard flash memory to define HyFlex functions, allowing developers to define, test, and update the soft macros.

HyFlex will be available in the second quarter of 2004 for $300 (10,000). The HySem and HyCount soft macros will be available in the third quarter for implementation in the HyFlex module and should become available in the fourth quarter for SOC. Standard products based on gate arrays should also become available in the fourth. HyWire bases pricing for intellectual-property cores on a license and royalty model, and standard components should sell for $200 (10,000).

HyWire Ltd, 972-9-8850575, www.hywire.com.