3D Interconnect Technology Coming to Light

By Jeff Chappell -- Electronic News, 4/15/2004

BURLINGAME, Calif. -- There are several start-ups and other smaller players in the chip industry that say they are poised to take advantage of an opportunity -- some would even call it an inflection point: building IC interconnects in three dimensions.

3D technology isn't a new concept; stacking multiple chips in a single package is not uncommon today. But many here at an International Sematech-sponsored technical conference are looking at stacking chips and connecting them through vias on the chips themselves. Connecting chips at the interconnect level is a relatively new wrinkle in the idea of building ICs in three dimensions, and the Austin-based consortium is making the technology a major thrust of its R&D efforts for the entire supply chain, from CAD software to tool benchmarking and process development.

The drivers behind 3D ICs in all of it various proposed incarnations is not knew at all: the demand for higher performance in smaller form factors. It also holds the promise of stacking dissimilar ICs in the same device or stacked chip -- not just logic and memory, but optical ICs and CMOS, for example.

Furthermore, by shortening the distance that electrical signals have to travel, 3D interconnect technology could provide the performance gains promised by Moore's Law while obviating the need for exotic materials potentially required in the deep sub-micron era, and the attendant integration headaches.

"All of those [materials] are on the list and none of them are easy, known solutions," said IBM researcher Kathryn Guarini, referring to materials such as low-k and ultra low-k interlayer dielectrics and high-k gate dielectrics called for on industry roadmaps beyond the 65nm node. Guarini is on the staff at IBM Corp.'s T.J. Watson Research Center and manager of its 45nm front-end integration group, and is heavily involved in the technology leader's 3D interconnect efforts.

If 3D ICs could eliminate the need for these exotic materials and their integration challenges, while still providing the necessary performance gains, it would certainly justify the development of 3D technology, Guarini suggested.

"That seems reasonable to me," said Robert Drost, principal research scientist with Sun Microsystems. While the use of these exotic materials enable device shrinks at advanced technology nodes they aren't necessarily providing performance gains, gains that could actually be realized through 3D interconnect technology, he said.

Starting Up on the 3D Frontier

But at the moment, 3D interconnect technology, while beyond nascent developmental stages, is still not in the technological bag. And it is this, coupled with its early promise, which makes the technology attractive not only to the likes of IBM and Sematech, but start-ups, IP companies, and others, as well.

Tezzaron Semiconductor, formerly Tachyon Semiconductor, is one such company. The company will be shipping low-volume 3D memory devices by the end of the year, with high-volume production to follow in 2005, said CTO Bob Patti. It has a 1Gbit DRAM based on 3D interconnect technology on the design drawing board, as well, but it has yet to be prototyped.

"DRAM is a wonderful device for 3D interconnect, because it doesn't get along with itself," Patti said, referring to the fact that the chips have both low leakage, high voltage bit cells and low voltage, high-speed I/Os. Memory speeds are also a performance bottleneck in integrated devices; memory operates much slower than the processor cores it is coupled with, he noted.

It's a gross simplification of the technologies involved, but essentially there are three different methods of stacking and bonding chips and connecting them at the via level: die to die, die to wafer, and wafer to wafer. Each has inherent advantages and disadvantages, particularly when it comes to thermal issues and testing.

Tezzaron is using a wafer-to-wafer bonding method it calls FaStack; it can achieve bonding tolerances using equipment by Austrian supplier EV Group to within a few microns and accuracy within half a micron, Patti said.

In addition to faster, lower-power memory, Tezzaron has realized a cost reduction by reducing the peripheral circuitry. It has been able to get rid of a significant part of the processing ICs needed for memory by connecting memory chips through 3D vias, Patti said.

He also claimed Tezzaron had overcome the yield issue inherent in stacking chips in this matter by utilizing its proprietary its embedded test and repair technology, Bi-STAR. The technology tests a chip at power up, and in terms of memory, can repair bit cells and other parts of the memory device through a remapping scheme, according to the company.

Meanwhile, Xanoptix is a device company that is concentrating on using 3D technology to combine devices on dissimilar substrates, such as standard CMOS and optical devices built on III-IV materials. Calling it Hybrid Integrated Circuit technology, the company founded in March 2000 says it has developed die-to-wafer and wafer-to-wafer bonding technology to accomplish that.

Its XTM series gigabit optical transceivers are based on the technology; the top product in the XTM series utilizes gallium arsenide- and silicon germanium-based ICs in a single device 8mm square and a data rate of 245 gigabits per second across 72 channels, according to John Trezza, CTO and founder of Xanoptix. The device has the same amount of circuitry as a network router used today that occupies several square feet, he claimed.

The company vies its Hybrid technology as a steppingstone between large products built on boards in a mainframe, such as that leading edge, million-dollar network router and a thousand dollar device that accomplish the same tasks.

Another start-up, Ziptronix, founded in October 2000 as a spin-off from North Carolina's Research Triangle Institute, is using die-to-wafer bonding to achieve 3D interconnects using off-the-shelf parts, utilizing the room-temperature bonding process at the institute, ZiROC. The company expects first silicon for its first 3D interconnect devices in the first part of 2005, said Bob Markunas, VP of market development for Ziptronix.

The company is targeting the mixed-signal market; it sees 3D vias as means of combining digital and analog ICs while overcoming the inherent speed and performance gaps inherent between analog and digital. "We think 3D offers a near perfect solution," Markunas said.

3D interconnect is engendering even bigger dreams than routers-on-a-chip and analog devices at digital speeds. Technology IP company Reveo Inc. envisions stacking as much as a 1,000 layers of ICs, creating such devices as terabit memory the size of a cubic centimeter, or a even a terabyte memory module that would fit in a shoebox.

The company has invented what it calls multi-filo-layer technology that involves selective bonding and peeling ultra thin layers of 10nm to 10-microns -- layers on which IC features have already been built, said Sadeg Faris, Reveo chairman and CEO. The technology can enable IC densities three orders of magnitude more than what can be accomplished with standard technology, Faris claimed.

He further said that the technology can be implemented with existing fabs and toolsets; an existing fab could be retrofitted for around $50 million to fabricate devices based on the multi filo-layer technology, he said.

Attendees at the conference seemed somewhat skeptical of the idea of what would essentially involve stacking hundreds of die, particularly when it comes to testing and determining known good die -- a key challenge to implementing 3D interconnect architectures. Much like memory bits can be addressed and reprogrammed to repair bad bits, the multi filo-layer stacks would be addressable, Faris suggested.