Synopsys: Position of strength

Synopsys relishes both the challenge and the responsibility of being the industry's leading EDA supplier.

by Terrence Lynch -- Movers and Shakers, 8/15/2003

Aart de Geus, Chairman and CEO, Synopsys

IT'S SAID THAT THE California gold rush produced few millionaires among the miners, but the men who sold the miners their tools did quite well. In a crippling market for electronics manufacturers, Synopsys, the leading supplier of EDA (electronic design automation) software, is doing just fine, thanks.

Amid the guarded answers and general gloom of the electronics industry, a conversation with Aart de Geus, Synopsys' chairman and CEO, is a tonic. He laughs easily and he's filled with infectious optimism.

"Our company is in the fortunate situation of having a prime seat, both as a supporter and sometimes as a leader in the thinking, but certainly at the table where the creativity is," de Geus says. "And that's just fun."

The company was started in 1986, offering electronic-design consulting and a single product: a "front-end" or logic-design tool. Since then, says de Geus, "the company has maintained a coherent strategy--never stopping the focus on technology, technology, technology."

In any given year, Synopsys spends approximately 25 percent of its total revenue on what de Geus calls "hardcore R&D." Over the years, it has developed "back-end" or physical-design tools and pioneered the development of static and formal design-verification tools as well.

The design-for-verification imperative led to a new business for Synopsys. As de Geus explains it, one way to simplify the task of determining whether a new design works the way it's supposed to is to build it, as much as possible, from pre-verified functional blocks. The technique is called IP (intellectual property) reuse.

"It's a very effective way of making design easier," de Geus says. "Over the last few years, we have grown our IP business as an adjacent business to the mainstay of EDA. And today, we are the No. 3 [provider] of commercial IP in the world."

The company has also grown through acquisitions. It merged with Avant! several years ago to become the industry's biggest full-line EDA supplier. Last March, Synopsys purchased Numerical Technologies, a maker of wafer-mask and lithography design tools. And in June, it acquired Innologic Systems, a leader in memory-testing technology.

"We can now go to a customer and say, 'You want to do implementation of a chip?' We have the architect services, the designer services, the plan makers, the builders, all the tools, etc," he explains. "It becomes more and more of an integrated, complete solution. In IC design, you have many complex interaction problems. Having a much more complete solution from one provider is of high value because it reduces risk."

Risk is a word that comes up often when speaking with de Geus. Asked if the industry's goal is to eliminate the need for multiple design iterations and fabrications, the so-called "second silicon," de Geus laughs.

"That's the 'don't screw up' goal," he says. "Anything you can do to reduce risk is always welcome. If you can reduce risk by having a more complete solution of the tools, that's great. If you can reduce risk by having really good support locally, that's great.

"The challenge there, and it's also the fun part, is that every time you reach the goal that it works right the first time, people say, 'Maybe I should have taken a little more risk and done a more ambitious chip or a little faster chip' and so on. In other words, you keep pushing the envelope, and that's why high-tech has moved forward so fast. People push the envelope to the tune of 40 percent [better performance] every year--that's Moore's Law."

Reminded that second silicon is expensive, that masks for deep submicron chips now cost $1 million or more, he quips, "If you get ulcers doing chip design, maybe you shouldn't be in that kitchen."

Ulcers are clearly not a problem for de Geus; he seems to relish the speed of evolution in electronic design and his company's place in making it happen.

"We're in this very exciting position, as the leader of our industry, to have both the challenge and the responsibility to set the direction and the tone and to have the vision to deal with all of these challenges," he says. "What we do has a huge impact on the success of our customers.

de Geus has coined the term "techonomics," sort of the vector sum of economics and technology that gives the industry direction. Asked about the future of the industry, he responds, "The rate of change of techonomics right now is very, very high. That's why you have major consolidation, major dislocations, major moves of some of the large players to invest while others can't.

"And you throw on top of that a fairly radical shift in how globally the markets and the investments are occurring, especially in regard to shifts in the Far East. You can see that in the next 10 years, we'll end up with an industry that's far different from what we have today."

As for that future industry's products, de Geus scoffs at the notion that Moore's Law may soon be repealed. He says he remembers being told that the laws of physics wouldn't allow circuit geometries below 1 micron.

"Just to put it in perspective, today we have just moved to 130 nm [0.13 micron]," he says. "After that there's 90 nm, then 65. So, yes, there may be a horizon with some harder limits. But creativity has been astonishing over the last 20 years.

"Maybe putting it in more balanced terms, I think that the economics of pushing the state-of-the-art are getting tougher. At the same time, I see that we have at least two design generations that are in good progress. So in the next four or five years, we'll still see dramatically more complex chips coming out."

And Synopsys' tools will help make that happen.